The thermomechanical reliability of surface mount components (SMCs) is closely related to the reflow soldering process. With the rise of board complexity, an optimal reflow profile must consider the mix of large and small components, the density of the components on the board, and the board dimensions. It has been a significant challenge to achieving uniform temperature on SMCs with different sizes and different thermal masses, such as capacitors, transistors, QFN, and BGA packages. To reflow large components such as BGA packages, the minimum reflow temperature should be reached, meanwhile, the temperature should not exceed the damaging temperature of the smaller or heat-sensitive components. The recommended reflow profile is defined as a band or process window. To achieve good quality soldering, the temperature applied to the solder under varied sizes of components should be within the recommended band. This paper introduces a numerical method based on a compact model to predict the reflow profile for bulky BGA packages. The impinging gas temperature is used as the boundary condition to predict the temperature distribution throughout a board with different sized components. The proper oven temperature setting to achieve the ideal profiles is obtained finally.

This article proposes a computational fluid dynamics-based machine learning (ML) model to set the temperature of a convection reflow oven and control conveyor speed. Due to the thermal mass variation of printed circuit boards (PCB) and surface mount components, the reflow recipe should be specified for each PCB assembly individually. Instead of relying on process engineers’ skills and experience, the machine learning model supported by heat transfer mechanisms provides a clear and logical path in the reflow recipe setup. An ideal recipe should let the largest component reach the minimum reflow temperature, meanwhile, the temperature cannot damage the small or heat-sensitive components. To simulate the reflow soldering process, the computational fluid dynamics (CFD) model was used after being validated with experiment results. A system was programmed to feed the output of the CFD model as the input to the ML model. Benefiting from the interpolation and fast response brought by ML models, we can rapidly obtain the results subjected to millions of recipes, which are the combination of preset temperatures of all the heating zones and the conveyor speed in the oven. Using a weighting filter function, the optimal recipe can be obtained. This methodology is especially beneficial to reflowing smaller batches of complex PCB assemblies with a big heat capacity.

The rapid advancement of artificial intelligence (AI) has propelled the demand for high-performance computing (HPC) systems capable of handling vast amounts of data. This necessitates improvements in data processing speed within System on Chip (SoC) units and efficient data transmission between SoC and high-bandwidth memory (HBM). Advanced packaging solutions, particularly the silicon interposer and organic interposer, have emerged to address these challenges. This paper delves into the thermo-mechanical performance of 2.5D packages with organic interposer, focusing on warpage management during fabrication and stress analysis induced by coefficient of thermal expansion (CTE) mismatches. The study employs finite element analysis (FEA) modeling to evaluate the impact of various factors on warpage behavior and stress level. Parametric studies on material selection and interposer geometric design reveal crucial insights. Specifically, reducing bridge die and redistribution layer (RDL) thickness mitigates warpage at the controlled collapse chip connection (C4) level, albeit with adverse effects on BGA level warpage. Material selection significantly influences warpage behavior. Organic materials with higher CTE reduces the mismatch between the interposer and the substrate but it is adverse for the interconnection between chiplets and interposer. Moreover, stress analysis indicates the organic interposer’s effectiveness in reducing interconnection stress compared to silicon interposers. This research contributes valuable insights into the design and optimization of advanced packages with bridges embedded organic interposer, providing guidelines for material selection and geometric design to enhance reliability and functionality. The findings facilitate the development of advanced packaging solutions capable of meeting the demands of AI-driven applications in challenging operational environments.

A reliable constitutive model for copper is important for simulating the thermomechanical behavior of copper TGV (Through Glass Via) in the glass interposer. This study presents a time-hardening model for the electroplated copper TGV. The material constants of copper in this model are evaluated by optimizing the experimental and numerical simulation results. In the experiment, the in-plane displacement of the glass was measured using 2D digital image correlation (DIC). The four material constants in the time hardening model were adjusted to ensure good agreement between the simulation results and the experimental results. This optimized time hardening model can be applied to copper TGVs over a wide range of temperatures (25 °C to 400 °C) and temperature ramp rates (4 °C/min to 50 °C/min).

As surface mount components shrink in size, smaller apertures on stencils during solder paste printing can lead to uneven solder volume on a single resistor. This can result in the formation of irregular solder shapes, which are often deemed acceptable criterion depending on assembly house. However, such irregularities can potentially introduce variations in the fatigue life of the surface mount component. This study employs experimental and numerical approaches to investigate the reliability of differently shaped SAC305 solder joints on a single chip resistor. Four distinct solder shapes, concave, straight, tiny convex, and convex, are generated using varying volumes of solder paste controlled by uniquely designed apertures on a stencil. Eight pairs of differently shaped solder joints are assembled to hold a chip resistor in place. The test assembly involves R1005 and R0402 soldered with SAC305 and undergoes thermal shock cycling. As a single chip resistor assembly consists of two solder joints connecting termination and pads, the effect of solder volume difference between two solder joints are investigated. The fatigue life corresponds to decrease as the solder volume difference increase as 40%, 80%, and 120%. Conversely, total volume of two solder joints in a single chip resistor increases in scenarios with the same volume difference between two solder joints. Experimental data and finite element analysis lead to a new set of Darveaux's constants specific to this assembly. This study provides guideline to control the solder paste volumes in relation to fatigue life and enables numerical solution using a new Darveaux's constants.