This article proposes a computational fluid dynamics-based machine learning (ML) model to set the temperature of a convection reflow oven and control conveyor speed. Due to the thermal mass variation of printed circuit boards (PCB) and surface mount components, the reflow recipe should be specified for each PCB assembly individually. Instead of relying on process engineers’ skills and experience, the machine learning model supported by heat transfer mechanisms provides a clear and logical path in the reflow recipe setup. An ideal recipe should let the largest component reach the minimum reflow temperature, meanwhile, the temperature cannot damage the small or heat-sensitive components. To simulate the reflow soldering process, the computational fluid dynamics (CFD) model was used after being validated with experiment results. A system was programmed to feed the output of the CFD model as the input to the ML model. Benefiting from the interpolation and fast response brought by ML models, we can rapidly obtain the results subjected to millions of recipes, which are the combination of preset temperatures of all the heating zones and the conveyor speed in the oven. Using a weighting filter function, the optimal recipe can be obtained. This methodology is especially beneficial to reflowing smaller batches of complex PCB assemblies with a big heat capacity.

The thermomechanical reliability of surface mount components (SMCs) is closely related to the reflow soldering process. With the rise of board complexity, an optimal reflow profile must consider the mix of large and small components, the density of the components on the board, and the board dimensions. It has been a significant challenge to achieving uniform temperature on SMCs with different sizes and different thermal masses, such as capacitors, transistors, QFN, and BGA packages. To reflow large components such as BGA packages, the minimum reflow temperature should be reached, meanwhile, the temperature should not exceed the damaging temperature of the smaller or heat-sensitive components. The recommended reflow profile is defined as a band or process window. To achieve good quality soldering, the temperature applied to the solder under varied sizes of components should be within the recommended band. This paper introduces a numerical method based on a compact model to predict the reflow profile for bulky BGA packages. The impinging gas temperature is used as the boundary condition to predict the temperature distribution throughout a board with different sized components. The proper oven temperature setting to achieve the ideal profiles is obtained finally.

A reliable constitutive model for copper is important for simulating the thermomechanical behavior of copper TGV (Through Glass Via) in the glass interposer. This study presents a time-hardening model for the electroplated copper TGV. The material constants of copper in this model are evaluated by optimizing the experimental and numerical simulation results. In the experiment, the in-plane displacement of the glass was measured using 2D digital image correlation (DIC). The four material constants in the time hardening model were adjusted to ensure good agreement between the simulation results and the experimental results. This optimized time hardening model can be applied to copper TGVs over a wide range of temperatures (25 °C to 400 °C) and temperature ramp rates (4 °C/min to 50 °C/min).

As surface mount components shrink in size, smaller apertures on stencils during solder paste printing can lead to uneven solder volume on a single resistor. This can result in the formation of irregular solder shapes, which are often deemed acceptable criterion depending on assembly house. However, such irregularities can potentially introduce variations in the fatigue life of the surface mount component. This study employs experimental and numerical approaches to investigate the reliability of differently shaped SAC305 solder joints on a single chip resistor. Four distinct solder shapes, concave, straight, tiny convex, and convex, are generated using varying volumes of solder paste controlled by uniquely designed apertures on a stencil. Eight pairs of differently shaped solder joints are assembled to hold a chip resistor in place. The test assembly involves R1005 and R0402 soldered with SAC305 and undergoes thermal shock cycling. As a single chip resistor assembly consists of two solder joints connecting termination and pads, the effect of solder volume difference between two solder joints are investigated. The fatigue life corresponds to decrease as the solder volume difference increase as 40%, 80%, and 120%. Conversely, total volume of two solder joints in a single chip resistor increases in scenarios with the same volume difference between two solder joints. Experimental data and finite element analysis lead to a new set of Darveaux's constants specific to this assembly. This study provides guideline to control the solder paste volumes in relation to fatigue life and enables numerical solution using a new Darveaux's constants.

Better understanding and control of residual stress in the chip build-up layer are becoming more and more important for the assembly process. To estimate the chip warpage and characterize the residual stress, different methods are proposed. However, most of them have high cost or some limitations for the upper build-up material. In this study, an innovative method is proposed to characterize the residual stress and predict the chip warpage behavior of different size chips at different temperatures. The method combines experimental inspection of chip warpage and finite element analysis. By reducing the silicon die thickness, the influence of residual stress in the build-up layer can be amplified. The residual stress can be obtained by inspecting the increased warpage when the silicon dies are reduced to different thicknesses. Correlating the thermal increase warpages of thinner chips can help characterize the effective modulus and coefficient of thermal expansion (CTE) of the build-up layer. This study can help better understand the commonly classified build-up layer information. The results show good agreements between two types of samples under the same upstream process flow.

By employing optimized outer packaging designs and materials, the impact energy can be effectively absorbed or dissipated, thereby preventing potential damage to interconnections and chips. This includes mitigating solder-joint fractures, chip cracks, pad cratering or lifting, and other mechanical stresses that commonly result from impact forces. To ensure that the internal ionic sensor remains resilient to moisture intrusion and can endure impact velocities of up to 30 mph, advanced packaging solutions have been developed. In this study, the ANSYS/LS-DYNA finite element analysis (FEA) tool was utilized to evaluate the performance of various packaging designs in minimizing the shock energy transferred to the printed circuit board (PCB). Modifications were made to the external foam packaging to increase the effective thickness and stiffness of the PCB, thus limiting its deformation under impact. These adjustments involved testing several configurations, including a two-layer foam system, a single-layer foam, and variations in the foam material’s stress-strain characteristics. The results demonstrated a significant reduction in PCB deformation—by 86.9%—with the final design achieving a deformation of just 52 μm, compared to 398.7 μm in the initial design. Furthermore, simulations of the final design were conducted for different drop orientations to ensure that out-of-plane deformations remained within the same order of magnitude, regardless of the drop direction.