In this paper, an irregular octagonal two-port MIMO patch antenna is designed specifically for New Radio (NR) 5G applications in the mid-band sub-6 GHz. The proposed antenna comprises an irregularly shaped patch antenna equipped with a regular 50-ohm feed line and a parasitic strip line antenna, and is partially grounded. Jeans material serves as a substrate with an effective dielectric constant of 1.6 and a thickness of 1 mm. This material is studied experimentally. The proposed antenna design undergoes analysis and optimization using the ANSYS HFSS tool. Furthermore, the design incorporates the influence of the slot on both the ground plane and the parasitic strip line to optimize performance, enhance isolation, and improve impedance matching among antenna elements. The dimensions of the jeans substrate are 40 mm × 50 mm. The simulated impedance bandwidth ranged from 3.6 GHz to 7 GHz and the measured bandwidth was slightly narrower, from 4.35 GHz to 7 GHz. The simulation results demonstrated an isolation level greater than 12 dB between antenna elements, while the measured results reached 28.5 dB, and the peak gain for this proposed antenna stood at 6.74 dB. These qualities made this proposed antenna suitable for various New Radio mid-band 5G wireless applications within the sub-6 GHz band, such as N79, Wi-Fi-5/6, V2X, and DSRC applications.

In this article, the photovoltaic thermal collector (PVT) have designed and fabricated using nanoparticle nanofluid. The cause of this is to check out the effect of using water and water-based totally graphene nanoplatelets at an awareness of 0.05 wt% on the performance of PVT structures. Outdoor assessments have been performed at quantity along with the float prices of 0.5 L/min and 1.0 L/min for the aforementioned nanofluids, respectively, using water as a reference fluid. The results that have been analyzed from an active angle confirmed and determined that, graphene water nanofluid achieved higher in phrases of photovoltaic active conversion, than water that might generate the first-class thermal performance sooner or later of the peak period of sun radiation and high mobile temperature. The inclusion of water in the PVT collector increases average daily electrical efficiency by 7.8%, and 8.5%at flow rates of 0.5 LPM and 1.0 LPM, respectively. Furthermore, using water in the PVT collector increases average daily thermal efficiency by 24.9%, and 26.3%at flow rates of 0.5 LPM and 1.0 LPM, respectively.

Multi supply voltage design technique is extensively used in modern VLSI designs to tradeoff energy and speed. Level shifters (LSs) are interfacing circuits that allow different voltage domains to be interfaced. This research article proposes a 0.125V- 0.325V input to 1.3V output-voltage Level Shifter that satisfies the requirements of Power, Delay, and voltage level shifting requirements of current IoT applications. The design was achieved using strong current limiters and potency pull down network. The proposed LS was implemented using 130nm technology and incurs static power of 6.6nW propagation delay of 10ns at the level shifting from 0.2V to 1.25V which is appropriate for IoT applications.

A level shifter (LS) appears to be highly efficient and effective in solving voltage contentions between deep sub-threshold and core voltage levels. An input voltage-level driven split-input inverter that can create common unconnected PMOS and NMOS transistors for the input inverter is proposed, which is powered and used at the input stage to achieve maximum conversion efficiency. Layout and simulation results across different corners have demonstrated that the proposed LS is highly useful for cutting-edge nanoscale applications. It can up-convert voltage from 0.2 V to 1.2 V and down-convert from 1.2 V to 0.2 V @ 1 MHz input pulse, with a level-up or level-down mean switching delay of 1.3 ns, and a power of 9.5 nW. Moreover, the LS occupies an area of 8 μm², which is a reasonably compact size compared to the typical LS designs. Overall, the proposed voltage LS design is an efficient and effective solution that could have an ample range of applications in IoT and biomedical, wireless sensor networks.

This paper presents a novel architecture of Femto power-delay super threshold voltage level shifter for network on chip voltage control, and developed using feedback topology for error aware interconnections data transmission. The proposed Level Shifter (LS) utilize eight MOS transistors with low aspect ratios for level up or level down. The developed LS can able to shift as low as 0.12 V to 1.25 V with tremendously reduction in delay and power consumptions. Implemented in 65 nm CMOS technology and the post-layout simulation substantiate the achievement of voltage translation. The proposed LS incurs energy per cycle 44 fJ during up shift, average level up and level down static power consumption is of 3.61 nW while VDDL is 0.3 V and VDDH is 1.2 V at the frequency of 1 MHz. The layout area of the proposed LS is 3.21 µm × 2.13 µm.