The thermodynamics of self-assembling systems are discussed in terms of the chemical interactions and the intermolecular forces between species. It is clear that there are both theoretical and practical limitations on the dimensions and the structural regularity of these systems. These considerations are made with reference to the microphase separation that occurs in block copolymer (BCP) systems. BCP systems self-assemble via a thermodynamic driven process where chemical dis-affinity between the blocks driving them part is balanced by a restorative force deriving from the chemical bond between the blocks. These systems are attracting much interest because of their possible role in nanoelectronic fabrication. This form of self-assembly can obtain highly regular nanopatterns in certain circumstances where the orientation and alignment of chemically distinct blocks can be guided through molecular interactions between the polymer and the surrounding interfaces. However, for this to be possible, great care must be taken to properly engineer the interactions between the surfaces and the polymer blocks. The optimum methods of structure directing are chemical pre-patterning (defining regions on the substrate of different chemistry) and graphoepitaxy (topographical alignment) but both centre on generating alignment through favourable chemical interactions. As in all self-assembling systems, the problems of defect formation must be considered and the origin of defects in these systems is explored. It is argued that in these nanostructures equilibrium defects are relatively few and largely originate from kinetic effects arising during film growth. Many defects also arise from the confinement of the systems when they are ‘directed’ by topography. The potential applications of these materials in electronics are discussed.

The advances in information and communication technologies have been largely predicated around the increases in computer processor power derived from the constant miniaturization (and consequent higher density) of individual transistors. Transistor design has been largely unchanged for many years and progress has been around scaling of the basic CMOS device. Scaling has been enabled by photolithography improvements (i.e. patterning) and secondary processing such as deposition, implantation, planarization, etc. Perhaps the most important of the secondary processes is the plasma etch methodology whereby the pattern created by lithography is ‘transferred’ to the surface via a selective etch to remove exposed material. However, plasma etch technologies face challenges as scaling continues. Maintaining absolute fidelity in pattern transfer at sub-16 nm dimensions will require advances in plasma technology (plasma sources, chamber design, etc) and chemistry (etch gases, flows, interactions with substrates, etc). In this paper, we illustrate some of these challenges by discussing the formation of ultra-small device structures from the directed self-assembly of block copolymers (BCPs) where nanopatterns are formed from the micro-phase separation of the system. The polymer pattern is transferred by a double etch procedure where one block is selectively removed and the remaining block acts as a resist pattern for silicon pattern transfer. Data are presented which shows that highly regular nanowire patterns of feature size below 20 nm can be created using etch optimization techniques and in this paper we demonstrate generation of crystalline silicon nanowire arrays with feature sizes below 8 nm. BCP techniques are demonstrated to be applicable from these ultra-small feature sizes to 40 nm dimensions. Etch profiles show rounding effects because etch selectivity in these nanoscale resist patterns is limited and the resist thickness rather low. The nanoscale nature of the topography generated also places high demands on developing new etch processes.