The medium- or high-entropy strategy has emerged as a new paradigm for designing high-performance piezoelectric ceramics. However, the effectiveness of this approach remains unclear to the development of high Curie temperature (TC) piezo-/ferroelectric materials with outstanding performance. To develop high-performance piezo-/ferroelectric materials suitable for high-temperature environments, in this work, we design a novel ceramic system based on a medium-entropy morphotropic phase boundary (ME-MPB) strategy. Piezo-/ferroelectric ceramics of the formula, Pb(Yb1/2Nb1/2)O3–Pb(In1/2Nb1/2)O3–PbTiO3, meeting the medium entropy criteria, were successfully synthesized using the conventional solid-state reaction method. The crystal structure, microstructure, dielectric, piezoelectric, and ferroelectric properties of the ceramics of the ME-MPB compositions were systematically investigated. X-ray diffraction and scanning electron microscopy analyses revealed that these ceramics possess a pure perovskite phase and dense microstructure. Notably, the prepared ceramics exhibited exceptional piezoelectric performance, with a high d33 up to 603 pC/N, a large strain of 0.20%, a high remanent polarization of 44.0 μC/cm2, and a high Curie temperature of 362 °C. This study demonstrates an effective design approach based on the ME-MPB strategy and points out a new pathway for developing high-performance materials for high-temperature applications as sensors, thereby expanding the research perspective on the design of medium-entropy piezo-/ferroelectric ceramics.

Electrical isolation devices are essential components for safeguarding the reliability of electronic systems under harsh conditions. Digital isolators are widely used in low-power circuits due to their high immunity to disturbances. In this paper, a capacitive digital isolator for high-efficiency power supply scenarios is proposed with a high common-mode transient immunity (CMTI) and high data transmission rate. The on–off keying (OOK) modulation technique is used to ensure a high speed and accurate signal transmission. A fully integrated high-voltage level-shift driver with an ns-scale delay is proposed for increasing the drive capacity. Post-simulation results in Cadence IC 6.1.7 with the standard 0.18 μm CMOS process show that the proposed architecture achieves a 25 Mbps data transmission rate and 15 ns typical propagation delay with output peak currents of 2 A/4 A, respectively. Meanwhile, a CMTI of more than 150 kV/μs is realized.

Learning-based three-dimensional (3D) generation increasingly targets computer-aided design (CAD) workflows, but visual fidelity, executable construction, persistent editing, and verified system behavior remain distinct claims. We review generation, reconstruction, and editing for mechanical and product CAD, using Generative Design Foundation Models (GDFMs) as an operational target combining reusable pretrained models with machine-checkable design state. Our output-centered taxonomy distinguishes visual/geometric priors, construction programs including constructive solid geometry (CSG), and evaluated CAD-native states. A Design Capability Profile records artifact and system-level tests; a separate Foundation Evidence Profile records pretraining breadth, transfer, adaptation efficiency, and backbone reuse. We propose representation choices for design workflows: construction programs expose explicit feature revisions, whereas boundary recovery targets state-centered reconstruction. Core examples distinguish supervised task adaptation, zero-shot cross-dataset classification, and joint task learning, while locating reuse in input encoders, design representations, tokenizers, or generation models. Dataset and benchmark comparisons expose complementary supervision, differing failure denominators, and distinct verification scopes. We recommend matching the representation, learned state, verifier, and inference budget to the intended workflow. GDFM is an evaluation target and research agenda, not a maturity label inferred from model size or output format.