Chengying Chen

Dr. Chengying Chen


Research Focus & Metrics

Academic Career Length

11Years (2016-Present)

(Calculated once Scilit publication data is synced: current year − year of first publication + 1)

Representative Publications

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25 June 2024 in Micromachines
Verified
Journal Article
Open access
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ZCZhifeng Chen
Zhifeng Chen
JCJiming Chen
Jiming Chen
WLWenli Liao
Wenli Liao
YZYuan Zhao
Yuan Zhao
JJJianhua Jiang
Jianhua Jiang
Chengying ChenChengying Chen
Chengying Chen
As the traditional silicon-based CMOS technology advances into the nanoscale stage, approaching its physical limits, the Carbon Nanotube Field-effect Transistor (CNTFET) is considered to be the most significant transistor technology beyond Moore’s era. The CNTFET has a quasi-one-dimensional structure so that the carrier can realize ballistic transport and has very high mobility. At the same time, a single CNTFET can integrate hundreds of nanowires as the conductive channels, enabling significant current transport capabilities even in low supply voltage, thereby providing a foundational basis for achieving nanoscale ultra-large-scale analog/logic circuits. This paper summarizes the development status of the CNTFET compact model and digital/analog/RF integrated circuits. The challenges faced by SPICE modeling and circuit design are analyzed. Meanwhile, solutions to these challenges and development trends of carbon-based transistors are discussed. Finally, the future application prospects of carbon-based integrated circuits are presented.

31 May 2023 in Electronics
Verified
Journal Article
Open access
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YHYUFEI HUANG
YUFEI HUANG
CCChengying Chen
Chengying Chen
YYYaguang Yang
Yaguang Yang
Chengying ChenChengying Chen
Chengying Chen
There is always a need for low-power, area-efficient VLSI (Very Large-Scale Integration) design and this need is increasing day by day. However, conventional design methods based on Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) devices and Complementary Metal-Oxide-Semiconductor Transistor (CMOS) technology cannot meet the performance requirements. The memristor, as a promising computing and memory integration device, offers a new research idea for conventional logic circuit structure and architecture innovation, given its non-volatility, scalability, low power consumption, fast switching speed, etc. This paper proposes a brief overview of the characteristics and current status of memristor-based logic circuits and analyzes their applications in numerical expression and memory. The benefits and drawbacks of various analog logic circuit structures are summarized and compared. In addition, some solution strategies for these issues are presented. Finally, this paper offers prospects for the applications of memristors in the logic implementation of large-scale memristor arrays, the novel structure of in-memory computing, and neural network computing.

1 May 2018 in Microelectronics Journal
Verified
Journal Article
Closed access
Chengying ChenChengying Chen
Chengying Chen
LCLiming Chen
Liming Chen
XWXinghua Wang
Xinghua Wang
FZFeng Zhang
Feng Zhang

30 December 2022 in Applied Sciences
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Journal Article
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JYJiayu Yin
Jiayu Yin
WLWenli Liao
Wenli Liao
YZYuyan Zhang
Yuyan Zhang
JJJianhua Jiang
Jianhua Jiang
Chengying ChenChengying Chen
Chengying Chen
Combining the advantages of low-power consumption of static random access memory (SRAM) with high stability and nonvolatile of resistive memory (RRAM), an improved 8T2R nonvolatile SRAM (nvSRAM) memory cell was proposed in this paper. In order to solve the problem that data cannot be stored when SRAM is powered off, RRAM technology was introduced into SRAM to realize an SRAM with nonvolatile function. The differential mode was adopted to improve the data restoration speed. Meanwhile, a pre-decoding technology was proposed to realize fast address decoding, and a voltage-mode sensitive amplifier was used to achieve fast amplification of two bit lines, so as to improve the reading speed of the memory. An 8kb nvSRAM was implemented with a CMOS 28 nm 1P9M process. The simulation results show that when the power supply voltage was 0.9 V, the static/read/write noise margin was 0.35 V, 0.16 V and 0.41 V, respectively. The data storage time was 0.21 ns, and restoration time was 0.18 ns. The time for the whole system to read 1 bit of data was 5.2 ns.

11 December 2018 in Circuits, Systems, and Signal Processing
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Chengying ChenChengying Chen
Chengying Chen
CCChengying Chen
Chengying Chen

15 August 2022 in Sensors
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Journal Article
Open access
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QRQirui Ren
Qirui Ren
Chengying ChenChengying Chen
Chengying Chen
DDDanian Dong
Danian Dong
XXXiaoxin Xu
Xiaoxin Xu
YCYong Chen
Yong Chen
FZFeng Zhang
Feng Zhang
This brief presents an analog front-end (AFE) for the detection of electroencephalogram (EEG) signals. The AFE is composed of four sections, chopper-stabilized amplifiers, ripple suppression circuit, RRAM-based lowpass FIR filter, and 8-bit SAR ADC. This is the first time that an RRAM-based lowpass FIR filter has been introduced in an EEG AFE, where the bio-plausible characteristics of RRAM are utilized to analyze signals in the analog domain with high efficiency. The preamp uses the symmetrical OTA structure, reducing power consumption while meeting gain requirements. The ripple suppression circuit greatly improves noise characteristics and offset voltage. The RRAM-based low-pass filter achieves a 40 Hz cutoff frequency, which is suitable for the analysis of EEG signals. The SAR ADC adopts a segmented capacitor structure, effectively reducing the capacitor switching power consumption. The chip prototype is designed in 40 nm CMOS technology. The overall power consumption is approximately 13 µW, achieving ultra-low-power operation.