Spike-timing dependent plasticity (STDP)-based spiking neural network (SNN) is a promising choice to realize unsupervised intelligent systems with a limited power budget. In addition to STDP, another two bio-inspired mechanisms of lateral inhibition and homeostasis are always implemented in the unsupervised training procedure of STDP-based SNNs. However, the existing methods to achieve lateral inhibition necessitate a great number of connections that are proportional to the square of the number of learning neurons, and the existing hardware solution of homeostasis demands complex circuits for each learning neuron, both of which challenge the hardware implementation of STDP-based SNNs. In this paper, we propose a novel SNN using memristor-based inhibitory synapses to realize the mechanisms of lateral inhibition and homeostasis with low hardware complexity. The proposed SNN can improve the network scalability by reducing the connection number for lateral inhibition from N2 to N and reduce the hardware overhead by leveraging the circuit of lateral inhibition to achieve homeostasis. Software simulations on the recognition task on MNIST dataset show that the proposed SNN achieves a ∼2 times higher learning efficiency with comparable accuracy. In addition, the challenging properties of realistic memristor devices, including limited number of resistive states, intrinsic parameter variation, and permanent open device, are added in the simulation to evaluate the robustness of our proposed approach.

For advanced technology nodes, the static random access memories (SRAMs) are highly vulnerable to the single-event upsets (SEUs), especially the multiple cell upsets (MCUs), by a high-energy ion strike, which is due to the small transistor size and close proximity of the sensitive regions. However, the narrow connection between the fin and the bulk region for fin field-effect transistor (FinFET) inhibits the charge collection compared to the planar transistor structure. In this work, heavy-ion tests were conducted for 16-nm bulk FinFET dual-port SRAMs at two high linear energy transfers (LETs) of 60 and 85 MeV $\cdot $ cm ² /mg. The non-saturating behavior of the SEU cross sections and event cross sections for a bit cell is observed even over the LET of 60 MeV $\cdot $ cm ² /mg due to the expanding of the sensitive area surrounding the array and the cutting-off area in the FinFET SRAM cells. The distribution curves of the MCU event probabilities for different MCU cluster sizes show that the single-bit upset (SBU) occupies the largest probability of all the single-event cluster sizes, which exhibits the inhibition capability of the Fin structure against the upsets induced by high-energy particles. The parasitic bipolar effect (PBE) is also serious for 16-nm FinFET SRAMs as former planar SRAM, but the charge-sharing effect is effectively inhibited due to the narrow connection between the fin and the bulk region for FinFET. Results presented in this article will help designers estimate the error correcting code (ECC) and interleaving design parameters for radiation-hardened SRAM designs at the 16-nm FinFET process.

For the purpose of fixing timing violations, static timing analysis (STA) of full-corners is repeatedly executed, which is time-consuming. Given a timing path, timing results at some corners (“dominant corners”) are utilized to predict timing at other corners (“non-dominant corners”), which can greatly shorten the runtime of STA. However, the huge number of combinations of the dominant corners and the wide difference in prediction accuracy make it difficult to apply multi-corner timing prediction to chip industrial design. In this paper, we propose a dominant corner selection strategy to quickly determine the dominant corner combination with high prediction accuracy, along with which a new multi-corner timing prediction process is established to speed up STA. Experimental results show that our method can not only effectively accelerate STA, but also ensure the high prediction accuracy of the prediction timing. On the public ITC’99 benchmark, the prediction accuracy of the dominant corner combination selected by the proposed method is up to 98.2%, which is an improvement of 15% compared to the state-of-the-art method. For industrial application, we apply our method by using timing results on only 2 dominant corners to predict the other 12 non-dominant corners, which accelerates the runtime of the timing closure process by more than 2×.

The effect of transistors in abutted rows on charge sharing is investigated by changing the configuration of the transistors in abutted rows in this work. 3D TCAD numerical simulations indicate that the existence of transistors in abutted rows can mitigate the occurring probability of charge sharing, especially charge sharing induced by ion striking at the vicinity of n-well contact. The simulations also indicate that the single event double transient (SEDT) pulse width is reduced obviously by the transistors in abutted rows for ion strike location near n-well contact. A 65 nm test chip was designed in commercial 65nm twin-well bulk CMOS process, and heavy-ion experiment was conducted. The experiment results agree well with the simulation results, which indicates that the effect of transistors in abutted rows on single event sensitivity and the occurring probability of charge sharing is more than 10%, and then considering the effect of transistors in abutted rows is necessary in nanometer technology.