For advanced technology nodes, the static random access memories (SRAMs) are highly vulnerable to the single-event upsets (SEUs), especially the multiple cell upsets (MCUs), by a high-energy ion strike, which is due to the small transistor size and close proximity of the sensitive regions. However, the narrow connection between the fin and the bulk region for fin field-effect transistor (FinFET) inhibits the charge collection compared to the planar transistor structure. In this work, heavy-ion tests were conducted for 16-nm bulk FinFET dual-port SRAMs at two high linear energy transfers (LETs) of 60 and 85 MeV $\cdot $ cm ² /mg. The non-saturating behavior of the SEU cross sections and event cross sections for a bit cell is observed even over the LET of 60 MeV $\cdot $ cm ² /mg due to the expanding of the sensitive area surrounding the array and the cutting-off area in the FinFET SRAM cells. The distribution curves of the MCU event probabilities for different MCU cluster sizes show that the single-bit upset (SBU) occupies the largest probability of all the single-event cluster sizes, which exhibits the inhibition capability of the Fin structure against the upsets induced by high-energy particles. The parasitic bipolar effect (PBE) is also serious for 16-nm FinFET SRAMs as former planar SRAM, but the charge-sharing effect is effectively inhibited due to the narrow connection between the fin and the bulk region for FinFET. Results presented in this article will help designers estimate the error correcting code (ECC) and interleaving design parameters for radiation-hardened SRAM designs at the 16-nm FinFET process.

As chip technologies scale down in size, multiple adjacent logic nodes are often affected by a single high-energy ion strike. The so-called pulse quenching effect, induced by single-event charge sharing collection, has a significant effect on single-event transients (SETs). In this paper, the effect of pulse quenching on SETs is quantitatively characterized in 65-nm twin-well and triple-well CMOS technologies. Two groups of heavy ion experiments on two inverter chains were performed for the characterizations, and the effect of pulse quenching on SETs was quantitatively analyzed in detail.

Analog single-event transient (ASET) and total ionizing dose (TID) characterization of a radiation-hardened bandgap voltage reference (BGR) is investigated in a 28-nm commercial bulk CMOS technology. Different radiation hardened by design (RHBD) techniques are used for ASET mitigation in the circuit and layout, and the circuit is optimized to ensure the BGR can still work correctly even using fast nMOS and slow pMOS for TID mitigation. Heavy-ion (linear energy transfer (LET) = 76.3 MeV $\cdot $ cm ² /mg) experiments show the maximum amplitude of positive (negative) ASET is just 30 mV (90 mV), and Co ⁶⁰ gamma-ray experiments show the maximum output voltage reduction is just 37 mV after 1.2 Mrad(Si) irradiation, and the final output voltage reduction is just 11 mV after 48 h of annealing. All of the experiments indicate that ASET is significantly mitigated by the RHBD techniques, and the BGR has naturally good TID response due to the design margin. The investigation also indicates that the proposed BGR is a good substitute for space application due to the excellent ASET and TID tolerance capability.

Total ionizing dose (TID) radiation response of the custom bandgap voltage reference (BGR) fabricated with 65 nm, 40 nm and 28 nm commercial bulk CMOS technologies is investigated. TID response is assessed employing Co-60 gamma ray source. The measurements indicate that the voltage reference is reduced by 5.67% in 28 nm, 0.56% in 40 nm and increased by 1.28% in 65 nm devices under irradiation up to 1.2 Mrad(Si) TID. After 48 hours of annealing, the voltage reference changes are just -1.84% in 28 nm, 0.14% in 40 nm and 1.14% in 65 nm. The obtained results demonstrate that the custom BGR has naturally superior TID response due to the circuit design margins.

In this paper, the dependence of sensing currents on various device parameters is comprehensively studied by simulating the complete crossbar array rather than its equivalent analytical model. The worst-case scenario for read operation is strictly analyzed and defined in terms of selected location and data pattern, respectively, based on the effect of parasitic sneak paths and interconnection resistance. It is shown that the worst-case data pattern depends on the trade-off between the shunting effect of the parasitic sneak paths and the current injection effect of the parasitic sneak leakage, thus requiring specific analysis in practical simulations. In dealing with that, we propose a concept of the threshold array size incorporating the trade-off to define the parameter-dependent worst-case data pattern. This figure-of-merit provides guidelines for the worst-case scenario analysis of the crossbar array read operations.

A hardened phase frequency detector employing double loop self-sampling technology is proposed for clock and data recovery. The PFD can remove the error state and maintain the correct state through use of the sampler. The laser experiment shows the threshold value of proposed PFD has been greatly improved.