We report on p and n-type vertical gate-all-around (GAA) nanowire (NW) and nanosheet (NS) FETs which offer attractive opportunities for ultra-scaled circuits. An in-depth evaluation is presented on the impact of doping and key device dimensions to improve the performance, variability, noise and reliability behavior for junctionless (JL) vs. inversion-mode (IM) vertical FETs built with an RMG scheme. The latter enables a novel concept to introduce stress in VFETs for enhanced mobility with up to a19% higher I ON predicted. SiGe/Si pillars and self-aligned spacers offer a solution to gate vertical (mis)alignment towards the S/D. As MRAM selector, VNS FETs can allow substantial area reduction (64% for 2VNS per cell; 3nm node design rules) vs. finFET based cells, with smaller read/write energy consumption and latency times.

Amorphous indium-gallium-zinc-oxide (a-IGZO) is demonstrated as an electron transport layer (ETL) in a high-performance organic photodetector (OPD). Dark current in the range of 10 nA/cm² at a bias voltage of −2 V and a high photoresponse in the visible spectrum were obtained in inverted OPDs with poly(3-hexylthiophene) and phenyl-C₆₁-butyric acid methyl ester active layer. The best results were obtained for the optimum a-IGZO thickness of 7.5 nm with specific detectivity of 3 × 10¹² Jones at the wavelength of 550 nm. The performance of the best OPD devices using a-IGZO was shown to be comparable to state-of-the-art devices based on TiO_x as ETL, with higher rectification achieved in reverse bias. Yield and reproducibility were also enhanced with a-IGZO, facilitating fabrication of large area OPDs. Furthermore, easier integration with IGZO-based readout backplanes can be envisioned, where the channel material can be used as photodiode buffer layer after additional treatment.

The main limitations of the current dynamic random access memory (DRAM) technology are its scalability and power consumption. These constraints can be overcome by using an In–Ga–Zn–oxide (IGZO) transistor that offers a low OFF-current and high scalability. For that, the IGZO device performance needs to be optimized, which includes increasing its $\textit{I}_{\biosc{on}}$ and $\textit{V}_{\text{TH}}$ . By combining experiments on scaled industry-relevant devices with ab initio calculations, we show that IGZO composition impacts $\textit{I}_{\biosc{on}}$ and $\textit{V}_{\text{TH}}$ through modifying channel mobility and carrier concentration. In the studied composition range, $\textit{I}_{\biosc{on}}$ increases with higher In % and lower Ga %, which is opposite to the $\textit{V}_{\text{TH}}$ trend. Scanning the whole IGZO composition space with ab initio calculations, we predict that films with In $<$ 10% and 20% $<$ Ga $<$ 80% might be beneficial for improving $\textit{I}_{\biosc{on}}$ and $\textit{V}_{\text{TH}}$ .

Total-ionizing-dose (TID) effects are evaluated in back-gated IGZO thin-film transistors irradiated under different gate biases. Negative-bias irradiation leads to worst-case degradation of TID response in these devices, primarily as a result of enhanced charge trapping in the SiO ₂ overlayer. The relatively small peak transconductance decrease after irradiation illustrates that IGZO transistors are much less sensitive to interface-trap buildup and other instabilities due to hydrogen release and transport than amorphous Si thin film transistors examined previously. The TID response of devices with different gate sizes is also investigated. No significant geometry dependence is observed, which is promising for future scaling down of the technology.

To search for the next semiconductor breakthrough, we calculate properties for binary amorphous systems and model to predict them for complex compositions.

While we demonstrate a back-gated (BG) amorphous Indium-Gallium-Zinc-Oxide (a-IGZO) transistors with a nearly ideal subthreshold slope (SS) ~ 60 mV/dec. However, SS degrades when a top-gated (TG) configuration is implemented. The energy distribution of traps inferred from temperature-dependent (T = 4 K - 300 K) and multi-frequency (f = 1 kHz - 100 kHz) admittance measurements, reveals a much higher trap density in TG devices. By analyzing the impact of each process step and conducting forming gas anneal (FGA) experiments, we reveal the role of hydrogen in the deterioration of the SS in the IGZO-based transistors.