Pierpaolo Mori

Mr. Pierpaolo Mori

orcid

Research Focus & Metrics

Academic Career Length

5Years (2022-Present)

(Calculated once Scilit publication data is synced: current year − year of first publication + 1)

Representative Publications

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16 September 2022 in Electronics
Verified
Journal Article
Open access
PDF file
EVEmanuele Valpreda
Emanuele Valpreda
PMPierpaolo Mori
Pierpaolo Mori
NFNael Fasfous
Nael Fasfous
MVManoj Rohit Vemparala
Manoj Rohit Vemparala
AFAlexander Frickenstein
Alexander Frickenstein
MMMaurizio Martina
Maurizio Martina
Energy and throughput efficient acceleration of convolutional neural networks (CNN) on devices with a strict power budget is achieved by leveraging different scheduling techniques to minimize data movement and maximize data reuse. Several dataflow mapping frameworks have been developed to explore the optimal scheduling of CNN layers on reconfigurable accelerators. However, previous works usually optimize each layer singularly, without leveraging the data reuse between the layers of CNNs. In this work, we present an analytical model to achieve efficient data reuse by searching for efficient scheduling of communication and computation across layers. We call this inter-layer scheduling framework HW-Flow-Fusion, as we explore the fused map-space of multiple layers sharing the available resources of the same accelerator, investigating the constraints and trade-offs of mapping the execution of multiple workloads with data dependencies. We propose a memory-efficient data reuse model, tiling, and resource partitioning strategies to fuse multiple layers without recomputation. Compared to standard single-layer scheduling, inter-layer scheduling can reduce the communication volume by 51% and 53% for selected VGG16-E and ResNet18 layers on a spatial array accelerator, and reduce the latency by 39% and 34% respectively, while also increasing the computation to communication ratio which improves the memory bandwidth efficiency.

19 November 2024 in Electronics
Verified
Journal Article
Open access
PDF file
PMPierpaolo Mori
Pierpaolo Mori
MRMohammad Shanur Rahman
Mohammad Shanur Rahman
LFLukas Frickenstein
Lukas Frickenstein
SSShambhavi Balamuthu Sampath
Shambhavi Balamuthu Sampath
MTMoritz Thoma
Moritz Thoma
CPClaudio Passerone
Claudio Passerone
The Winograd algorithm reduces the computational complexity of convolutional neural networks (CNNs) by minimizing the number of multiplications required for convolutions, making it particularly suitable for resource-constrained edge devices. Concurrently, most edge hardware accelerators utilize 8-bit integer arithmetic to enhance energy efficiency and reduce inference latency, requiring the quantization of CNNs before deployment. Combining Winograd-based convolution with quantization offers the potential for both performance acceleration and reduced energy consumption. However, prior research has identified significant challenges in this combination, particularly due to numerical instability and substantial accuracy degradation caused by the transformations required in the Winograd domain, making the two techniques incompatible on edge hardware. In this work, we describe our latest training scheme, which addresses these challenges, enabling the successful integration of Winograd-accelerated convolution with low-precision quantization while maintaining high task-related accuracy. Our approach mitigates the numerical instability typically introduced during the transformation, ensuring compatibility between the two techniques. Additionally, we extend our work by presenting a custom-optimized CUDA implementation of quantized Winograd convolution for NVIDIA edge GPUs. This implementation takes full advantage of the proposed training scheme, achieving both high computational efficiency and accuracy, making it a compelling solution for edge-based AI applications. Our training approach enables significant MAC reduction with minimal impact on prediction quality. Furthermore, our hardware results demonstrate up to a 3.4× latency reduction for specific layers, and a 1.44× overall reduction in latency for the entire DeepLabV3 model, compared to the standard implementation.

30 January 2024
Verified
Book Chapter
Closed access
PDF file
LFLukas Frickenstein
Lukas Frickenstein
SSShambhavi Balamuthu Sampath
Shambhavi Balamuthu Sampath
PMPierpaolo Mori
Pierpaolo Mori
MVManoj-Rohit Vemparala
Manoj-Rohit Vemparala
NFNael Fasfous
Nael Fasfous
WSWalter Stechele
Walter Stechele

31 July 2024
Verified
Book Chapter
Closed access
PDF file
LFLukas Frickenstein
Lukas Frickenstein
MTMoritz Thoma
Moritz Thoma
PMPierpaolo Mori
Pierpaolo Mori
SSShambhavi Balamuthu Sampath
Shambhavi Balamuthu Sampath
NFNael Fasfous
Nael Fasfous
WSWalter Stechele
Walter Stechele