In recent years, there has been a tremendous increase in the use of connected devices as part of the so-called Internet of Things (IoT), both in private spaces and the industry. Integrated distributed systems have shown many benefits compared to isolated devices. However, exposing industrial infrastructure to the global Internet also generates security challenges that need to be addressed to benefit from tighter systems integration and reduced reaction times. Machine learning algorithms have demonstrated their capacity to detect sophisticated cyber attack patterns. However, they often consume significant amounts of memory, computing resources, and scarce energy. Furthermore, their training relies on the availability of datasets that accurately represent real-world data traffic subject to cyber attacks. Network attacks are relatively rare events, as is reflected in the distribution of typical training datasets. Such imbalanced datasets can bias the training of a neural network and prevent it from successfully detecting underrepresented attack samples, generally known as the problem of imbalanced learning. This paper presents a shallow neural network comprising only 110 ReLU-activated artificial neurons capable of detecting representative attacks observed on a communication network. To enable the training of such small neural networks, we propose an improved attack-sharing loss function to cope with imbalanced learning. We demonstrate that our proposed solution can detect network attacks with an F1 score above 99% for various attacks found in current intrusion detection system datasets, focusing on IoT device communication. We further show that our solution can reduce the false negative detection rate of our proposed shallow network and thus further improve network security while enabling processing at line rate in low-complexity network intrusion systems.

A paradigm shift is apparent in Chip Multiprocessor (CMP) design, as the new performance bottleneck is becoming communication rather than computation. It is widely provisioned that number of cores on a single chip will reach thousands in a decade. Thus, new high rate interconnects such as optical or RF have been proposed by various researchers. However, these interconnect structures fail to provide essential requirements of heterogeneous on-chip traffic; bandwidth reconfigurability and broadcast support with a low complex design. In this paper we investigate the feasibility of a new Orthogonal Frequency Division Multiple Access (OFDMA) RF interconnect for the first time to the best of our knowledge. In addition we provide a novel dynamic bandwidth arbitration and modulation order selection policy, that is designed regarding the bimodal on-chip packets. The proposed approach decreases the average latency up to 3.5 times compared to conventional static approach.

Avionics is one kind of domain where prevention prevails. Nonetheless failures occur, sometimes due to pilot misreacting, flooded in information. Sometimes information itself would be better verified than trusted. To avoid some kind of failure, it has been thought to add,in midst of the ARINC664 aircraft data network, a new kind of monitoring.

In this paper, a novel methodology for high-level modeling of bus communication in embedded systems is introduced. It allows the dynamic evaluation of their signal integrity (SI) characteristics at the virtual prototyping step (i.e., before physical realization). The method is based on the association of functional and nonfunctional modules. Functional modules represent the ideal behavior of the system, while nonfunctional modules use neural networks to model SI effects. This approach was implemented in SystemC-AMS, using the timed data flow model of computation. The method is illustrated by a Universal Serial Bus (USB) 3.0 application, where modular and parameterizable models are introduced. The method achieved good accuracy (<;5%) while allowing significant simulation speedup (up to 2000 times), compared with SPICE-based reference models. This methodology can be used to perform an early SI analysis in the virtual prototyping of bus communication in the embedded systems.