Analytical models for vias and traces are presented for simulation of multilayer interconnects at the package and printed circuit board levels. Vias are modeled using an analytical formulation for the parallel-plate impedance and capacitive elements, whereas the trace-via transitions are described by modal decomposition. It is shown that the models can be applied to efficiently simulate a wide range of structures. Different scenarios are analyzed including thru-hole and buried vias, power vias, and coupled traces routed into different layers. By virtue of the modal decomposition, the proposed method is general enough to handle structures with mixed reference planes. For the first time, these models have been validated against full-wave methods and measurements up to 40 GHz. An improvement on the computation speed of at least two orders of magnitude has been observed with respect to full-wave simulations.

The via-plate capacitance for a via transition to a multilayer printed circuit board is evaluated analytically in terms of higher order parallel-plate modes. The Green's function in a bounded coaxial cavity for a concentric magnetic ring current is first derived by introducing reflection coefficients for cylindrical waves at the inner and outer cavity walls. These walls can be perfect electric conductor (PEC)/perfect magnetic conductor(PMC) or a nonreflective perfectly matched layer. By further assuming a magnetic frill current on the via-hole in the metal plate, an analytical formula is derived for the via barrel-plate capacitance by summing the higher order modes in the bounded coaxial cavity. The convergence of the formula with the number of modes, as well as with the radius of the outer PEC/PMC wall is discussed. The analytical formula is validated by both quasi-static numerical methods and measurements. Furthermore, the formula allows the investigation of the frequency dependence of the via-plate capacitance, which is not possible with quasi-static methods.

Through silicon via (TSV)-based 3-D integrated circuit has introduced the solution to limitlessly growing demand on high system bandwidth, low power consumption, and small form factor of electronic devices. As the system design aims for higher performance, the physical dimensions of the channels are continuously decreasing. With TSV diameter of less than 10 μm and pitch of several tens of micrometers, the I/O count has increased up to the order of tens of thousands for wide bandwidth data transmission. However, without highly precise fabrication process, such small structures are susceptible to a variety of defects. For the first time, in this paper, we propose a noninvasive defect analysis method for high-speed TSV channel. With designed and fabricated test vehicles, the proposed method is demonstrated with S-parameter and time-domain reflectometry measurement results. In addition, we present equivalent circuit models of TSV daisy-chain structures, including the circuit components for open defect and short defect. With characterized dominant factors in each frequency range, S ₁₁ is analyzed to distinguish and locate the defects by the amount of capacitance, resistance, and inductance that the signal experiences. S-parameter measurement sufficiently allows high-frequency defect analysis of TSV channel without destroying the test sample. We experimentally verified the accuracy of the suggested model by comparing the S-parameter results from circuit simulations and measurements. Finally, the model is modified to discuss the effects of open defect and short defect on the electrical characteristics of TSV channel.

A cascaded S-parameter method is proposed in this paper for signal/power integrity analysis of multiple vias in a multilayer printed circuit board (PCB). The proposed method enables efficient and accurate construction and simulation of physics-based via model for complex multilayer PCB structures involving vias. The physics-based via model describes the parasitic effects near each via region as well as mutual coupling among different vias. In this model, each via portion between two parallel plates is regarded as a three-port network with two coaxial ports and one radial port between the two plates. A procedure is first developed to obtain the S-parameters of a single plate pair, which combine the three-port via networks with the impedance matrix of the parallel-plate pair. Once the S-parameters of each plate pair are obtained, an assembling technique for cascading microwave networks is further developed. The method proposed in this paper has been validated by both simulations with a commercial circuit simulator and measurements.

In this paper, a simple synthesis procedure to design planar electromagnetic bandgap (EBG) structures is proposed. It is based on the consideration of the excess of inductance of a patterned plane with respect to a solid one. The planar EBG structure is sized from the bandgap starting and ending frequencies, and few others specifications employing a closed form formulation. The proposed method is also suitable for the design of embedded planar EBG. The procedure is validated by using measured and numerically computed results.

The aim of this paper is to present a novel and compact transmit/receive module (TRM) for enhancing antenna performances to be employed in space applications. The key advancement is the use of a 3-D technology which, to the best of our knowledge, would be for the first time introduced in the space industry for hermetically packaging RF modules. The 3-D module development is based on the highly demanding specifications of space active electronically steerable antennas (AESAs); the TRM consists of two ``submodules'' electrically connected by an ad hoc interposer. The complete electrical design process, together with a comprehensive discussion on electromagnetic, mechanical, and thermal aspects, is presented, and the achieved module performances such as gain and return losses are detailed. Moreover, several manufactured samples are measured to validate the simulated design, and the excellent results in terms of gain, noise figure, and output power fulfilling the target specs are presented and discussed. The presented data, characterized by a limited variability among the 10 measured samples, make the proposed design and the manufacturing process a good candidate in terms of potential reliability for building the next generation of high-performance space AESA.