Breakdown voltage (BV) shifting behavior induced by total-ionizing-dose (TID) irradiation is investigated for high-voltage SOI LDMOS, in this letter. The BV increase caused by irradiation is present for the first time, and the degradation mechanism is revealed by modeling and simulation. Irradiation-induced electric field modulation exerts an impact on the competition between the lateral BV and vertical BV and results in BV shifting. The dielectric field is enhanced by irradiation-induced positive oxide trapped charges in the BOX layer, which is responsible for the BV increasing after irradiation. A TID radiation hardening approach is proposed so that the lateral BV is required to be properly higher than vertical BV instead of pursuing equality.

In this article, total-ionizing-dose (TID) response for dynamic threshold voltage ( $\textit{V}_{\text{TH}}\text{)}$ in p-GaN gate high electron mobility transistors (HEMTs) is studied. A nonmonotonic dependence of $\textit{V}_{\text{TH}}$ on dynamic gate stress is observed and the impact mechanism of Irradiation damages in the metal/p-GaN/AlGaN system is revealed. At the p-GaN/AlGaN interface, the new interface traps built by irradiation cause more positive $\textit{V}_{\text{TH}}$ shift. At the metal/p-GaN Schottky junction, irradiation damage related to possible nitrogen vacancies would enhance the hole-injection with increasing gate current. The hole-injection enhancement gives rise to stronger optical pumping and more holes trapped in the AlGaN barrier, causing more negative $\textit{V}_{\text{TH}}$ shift. Irradiation damages would change the competition relationship between electron trapping and the hole-injection, which is responsible for the nonmonotonic $\textit{V}_{\text{TH}}$ shift. The increase of gate current, drain leakage, and change of gate capacitance is presented to verify the mechanism.

In this paper, total ionizing dose (TID) effect is investigated in the 30 V split-gate trench (SGT) VDMOS. The complex trench structure, including gate oxide, split-gate oxide and isolation oxide, is carefully studied to reveal the degradation mechanisms. Due to the multi-oxidation and annealing processes, the trench structure suffers serious oxide defeats. Analytical result shows a larger trapping efficiency (fot) compared with planar gate technology, leading to significant Vth shifts and subthreshold leakage. Meanwhile, irradiation-induced trapped charges in the split-gate oxide have a great influence on the electric field profile in bulk, which gives rise to BV degradation. Experiment result shows that BV presents a gradient descent and drops to as low as 14 V at 100 krad(Si). Through TCAD simulation and analytical calculation, these TID responses are evaluated, and three approaches have been proposed for the radiation hardness of SGT VDMOS.

A novel snapback-free Silicon-Controlled Rectifier (SFSCR) with P-type zener implantation (ZP) is developed in 0.5 μm Bipolar CMOS DMOS (BCD) technology for latch-up immune high-voltage (HV) electrostatic discharge (ESD) protection. The inherent snapback of SCR is successfully suppressed by the novel ZP technique. But, it also brings about a seriously degradation on failure current (It2), as compared to the regular low holding voltage (Vh) device. In order to mitigate such a degradation, a novel layout terminal is proposed. According to the transmission line pulse (TLP) test results, the It2 of the SFSCR with new layout is increased 58.5%, while the on-state resistance (Ron) is reduced 48.7% under the same layout area. By the comprehensive comparison, the SFSCR is proved to be a potential HV ESD solution.

In this article, an improved model on buried-oxide (BOX) damage induced by total-ionizing-dose (TID) effect considering positive oxide trapped charge ( N _ot ) generated in silicon on insulator (SOI)/BOX interface under negative electric field bias (field lines perpendicular to the SOI/BOX interface pointing from the top to the bottom of the BOX) and N _ot saturation effect is proposed and adopted in accurate simulated analysis to predict the postirradiation device behavior. Moreover, the mechanism of high-voltage (HV) SOI lateral double diffused metal oxide semiconductor field effect transistor (LDMOS) degradation during irradiation is also revealed by the proposed accurate simulation method. Tolerance design for radiation-hardened HV SOI LDMOS is discussed with the aid of the presented model. The tradeoff between postirradiation electrical characteristics and fresh electrical characteristics should be taken into account to meet the radiation hardening requirement. The radiation-hardened-by-design LDMOS introduced in this article keeps an OFF-state breakdown voltage above 120 V at D = 500 krad(Si) with operating voltage equal to 80 V, which is fabricated on a commercial SOI substrate material with plain interface quality parameters. The corresponding hardening strategy is also given.

Total-ionizing-dose radiation response for 600V ultra-thin layer SOI LDMOS transistor is investigated. Radiation conduction modulation model is proposed to reveal the degradation mechanism of conduction current and breakdown voltage. Multi-interface irradiation damage cause positive net trapped charge, which reduces on-resistance equivalently and enhance conduction current. Meanwhile, they suppress the depletion in the drift region at off-state and then decrease breakdown voltage. Based on the model, irradiation induced net trapped charge density are extracted to evaluate the irradiation damage in drift region.