A novel superjunction (SJ) LDMOS (>950 V) with a thin layer SOI (T-SJ LDMOS) combining the advantage of low specific on-resistance Ron,sp of the SJ and the high breakdown voltage VB of the thin SOI is proposed and experimentally demonstrated in this letter. Based on our previously developed equivalent substrate (ES) model, the optimized SJ endows the device with a respectably reduced Ron,sp without sacrificing VB. Meanwhile, the thin layer SOI is designed with the enhanced dielectric layer field (ENDIF) principle to carry out a high VB. The experimental results exhibit a Ron,sp of 145 mΩ·cm² with a VB of 977 V. This represents a reduction in Ron,sp by 18.1% when compared with the theoretical Ron,spα 2.5 “silicon limit”.

A novel high voltage ultra-thin silicon on insulator (SOI) lateral double diffused metal oxide semiconductor field effect transistor (LDMOS) with a sectional linearly doped drift region is proposed and experimentally realized in this letter. The new device features a sectional linear doping (SLD) in a 0.17 μm SOI layer with a source field plate covering the full drift region. Low specific on-resistance Ron,sp is obtained by increasing the local doping concentration of the high resistance region. An analytical model is developed to provide the design guidance for the thin SOI devices with the field plate. The experimental results of the SOI SLD-LDMOS demonstrate that the new device shows a high breakdown voltage VB of 960 V with a superior figure of merit (FOM = VB 2 / Ron,sp) of 5.98 MW/cm2 when comparing with other reported thin SOI devices. Good agreements are observed between the model and the experimental results.

Breakdown voltage (BV) shifting behavior induced by total-ionizing-dose (TID) irradiation is investigated for high-voltage SOI LDMOS, in this letter. The BV increase caused by irradiation is present for the first time, and the degradation mechanism is revealed by modeling and simulation. Irradiation-induced electric field modulation exerts an impact on the competition between the lateral BV and vertical BV and results in BV shifting. The dielectric field is enhanced by irradiation-induced positive oxide trapped charges in the BOX layer, which is responsible for the BV increasing after irradiation. A TID radiation hardening approach is proposed so that the lateral BV is required to be properly higher than vertical BV instead of pursuing equality.

In this article, total-ionizing-dose (TID) response for dynamic threshold voltage ( $\textit{V}_{\text{TH}}\text{)}$ in p-GaN gate high electron mobility transistors (HEMTs) is studied. A nonmonotonic dependence of $\textit{V}_{\text{TH}}$ on dynamic gate stress is observed and the impact mechanism of Irradiation damages in the metal/p-GaN/AlGaN system is revealed. At the p-GaN/AlGaN interface, the new interface traps built by irradiation cause more positive $\textit{V}_{\text{TH}}$ shift. At the metal/p-GaN Schottky junction, irradiation damage related to possible nitrogen vacancies would enhance the hole-injection with increasing gate current. The hole-injection enhancement gives rise to stronger optical pumping and more holes trapped in the AlGaN barrier, causing more negative $\textit{V}_{\text{TH}}$ shift. Irradiation damages would change the competition relationship between electron trapping and the hole-injection, which is responsible for the nonmonotonic $\textit{V}_{\text{TH}}$ shift. The increase of gate current, drain leakage, and change of gate capacitance is presented to verify the mechanism.

In this paper, total ionizing dose (TID) effect is investigated in the 30 V split-gate trench (SGT) VDMOS. The complex trench structure, including gate oxide, split-gate oxide and isolation oxide, is carefully studied to reveal the degradation mechanisms. Due to the multi-oxidation and annealing processes, the trench structure suffers serious oxide defeats. Analytical result shows a larger trapping efficiency (fot) compared with planar gate technology, leading to significant Vth shifts and subthreshold leakage. Meanwhile, irradiation-induced trapped charges in the split-gate oxide have a great influence on the electric field profile in bulk, which gives rise to BV degradation. Experiment result shows that BV presents a gradient descent and drops to as low as 14 V at 100 krad(Si). Through TCAD simulation and analytical calculation, these TID responses are evaluated, and three approaches have been proposed for the radiation hardness of SGT VDMOS.

A novel high-voltage thin layer SOI technology based on 1-mum-thick silicon layer and 2-mum-thick buried oxide layer for driving color plasma display panels (PDP) has been developed. High-voltage pLDMOS with thick gate oxide, high- voltage nLDMOS, and low-voltage CMOS are compatible with LOCOS isolation. The proposed technology includes two aspects: first, an implantation after field oxide (IFO) technology is developed for achieving shallow junction depth of p-field region to avoid punch-through breakdown induced by back-gate (BG) effect of pLDMOS; second, conforming technology of isolation and oxidation is adopted for forming thick gate oxide of high-voltage pLDMOS, field oxide isolation of low-voltage CMOS, and full dielectric isolation between high-voltage and low-voltage CMOS simultaneously without additional mask and process. Compared with conventional technology of junction or trench isolation, the new high-voltage thin layer SOI technology achieves better process compatibility with lower process complexity and lower parasitic capacitance. A PDP data driver IC using the developed technology shows that the rise and fall times of the output stages are about 230 ns and 160 ns respectively under the supply voltage of 80 V and load capacitance of 50 pF.