The von Neumann architecture is no longer sufficient for handling large-scale data. In-memory computing has emerged as the potent method for breaking through the memory bottleneck. A new 10T SRAM bitcell with row and column control lines called RC-SRAM is proposed in this article. The architecture based on RC-SRAM can achieve bi-directional and operand-controllable logic-in-memory and search operations through different signal configurations, which can comprehensively respond to various occasions and needs. Moreover, we propose threshold-controlled logic gates for sensing, which effectively reduces the circuit area and improves accuracy. We validate the RC-SRAM with a 28 nm CMOS technology, and the results show that the circuits are not only full featured and flexible for customization but also have a significant increase in the working frequency. At VDD = 0.9 V and T = 25 °C, the bi-directional search frequency is up to 775 MHz and 567 MHz, and the speeds for row and column Boolean logic reach 759 MHz and 683 MHz.

Offset voltage ($V_{\mathrm{OS}}$) is a critical parameter of sense amplifiers (SAs), determining both the read reliability and performance of SRAM. This paper proposes SC-DISBSA, a low-$V_{\mathrm{OS}}$ SA that combines self-adaptive calibration with dynamic body bias technology. Based on the linear relationship between the transfer gate voltage and $V_{\mathrm{OS}}$, a three-step self-adaptive calibration algorithm is established. Supported by the calibration control circuit, this approach quantitatively calibrates circuit mismatch while dynamic body bias further suppresses remaining variations. Under a 28 nm CMOS process, the $V_{\mathrm{OS}}$ standard deviation (${\sigma }_{\mathrm{OS}}$) of SC-DISBSA remains below 3.1 mV across a 0.7 V to 1.1 V supply range, representing reductions of 49.9% and 69.3% compared to the voltage-latch SA (VLSA) and current-latch SA (CLSA), respectively. At a typical case (TT/0.9 V/27 °C) with a BL differential ($\Delta V_{\mathrm{BL}}$) of $6{\sigma }_{\mathrm{OS}}$, SC-DISBSA reduces the required bitline discharge delay by 51.7% and improves average read sensing power by 24.9% compared to VLSA. By adopting an non-conventional bitline power supply strategy, SC-DISBSA decreases worst case (FF/1.1 V/125 °C) static power by 36.8% relative to VLSA. Additionally, it reduces gate area by 18.9%. Overall, SC-DISBSA effectively optimizes SRAM read latency and power efficiency.