In this Letter, a high-power diode-side-pumped Nd:YAG laser emitting at $1338\mathrm{nm}$ is described. The output characteristics of the laser using the different output couplers for both the cw mode and the Q-switched mode have been studied. With a pumping power of $555\mathrm{W}$, the average output power decreases from $70\mathrm{W}$ at $50\mathrm{kHz}\text{to}55\mathrm{W}$ (slope efficiency 21.2%, optical conversion efficiency 10%) at $5\mathrm{kHz}$. The highest peak power is up to $73\mathrm{kW}$ with the pulse duration of $150\mathrm{ns}$ at the repetition rate of $5\mathrm{kHz}$. When operated in cw mode, the output power of $100.5\mathrm{W}$ was achieved, corresponding with the optical slope efficiency of 36%.

In this work, the electrostatic and radio frequency performances of 22 nm FDSOI nMOSFETs with p-type or n-type doped backplane (BP, highly doped layer of silicon below thin buried oxide) at cryogenic temperatures have been investigated. Greater enhancement of drain current $\text{I}_{\mathrm{ d}}$ , maximum transconductance $\text{g}_{\mathrm{ m,max}}$ and threshold voltage $\text{V}_{\mathrm{ TH}}$ values have been demonstrated at liquid nitrogen temperatures. Furthermore, FDSOI nMOSFETs with n-type BP achieve the maximum transconductance at lower bias voltage and smaller $\text{V}_{\mathrm{ ZTC}}$ , which is mainly due to its small threshold voltage. The variation of threshold voltage of BP-p devices is greater with the decrease of temperature. About 40% improvement of $\text{f}_{\mathrm{ T}}$ and 30% improvement of $\text{f}_{\mathrm{ max}}$ depended on the $\text{W}_{\mathrm{ f}}$ of devices have been shown. Relevant small-signal parameters (e.g., transconductance $\text{g}_{\mathrm{ m}}$ , gate capacitance $\text{C}_{\mathrm{ gg}}$ , gate resistance $\text{R}_{\mathrm{ g}}$ and output conductance $\text{g}_{\mathrm{ ds}}$ ) are also extracted for comparison and analysis. This study presents both 22 nm FDSOI nMOSFETs with p-type or n-type backplane as good candidates for cryogenic applications down to 77 K, and especially, BP-n FDSOI are more suitable for low power operation applications because of their lower threshold voltage. Similar $\text{g}_{\mathrm{ m.max}}$ and the peak values of RF FOMs can be obtained at lower bias voltage compared with BP-p devices.

A compact model for tunnel diode body contact (TDBC) silicon-on-insulator (SOI) n-MOSFETs was developed in this paper. The compact model is implemented in Verilog-A to simulate the dc and radio frequency (RF) performance of a TDBC SOI MOSFET. The TDBC SOI MOSFETs are successfully fabricated and are used to measure important transistor electrical parameters. The investigation results reveal that TDBC structure suppresses floating body effects (FBEs) as well as T-gate body (TB) contact structure and shows significant improvement in RF performance without introducing additional parasitic capacitances compared with the TB device. Kink phenomena and an abnormal subthreshold swing originating from FBEs are sufficiently suppressed. It is demonstrated that the TDBC SOI MOSFETs provide a promising concept for digital, analog, and RF applications. The outputs from this analytic model are in fair agreement with the TDBC experimental data, which validates the effectiveness and robustness of the compact model for TDBC SOI technology. Finally, good accuracy ensures that the proposed model is applicable for the implementation in circuit simulation tools.

On the basis of a detailed discussion of the development of total ionizing dose (TID) effect model, a new commercial-model-independent TID modeling approach for partially depleted silicon-on-insulator metal-oxide-semiconductor field effect transistors is developed. An exponential approximation is proposed to simplify the trap charge calculation. Irradiation experiments with Co gamma rays for IO and core devices are performed to validate the simulation results. An excellent agreement of measurement with the simulation results is observed.

The von Neumann architecture is no longer sufficient for handling large-scale data. In-memory computing has emerged as the potent method for breaking through the memory bottleneck. A new 10T SRAM bitcell with row and column control lines called RC-SRAM is proposed in this article. The architecture based on RC-SRAM can achieve bi-directional and operand-controllable logic-in-memory and search operations through different signal configurations, which can comprehensively respond to various occasions and needs. Moreover, we propose threshold-controlled logic gates for sensing, which effectively reduces the circuit area and improves accuracy. We validate the RC-SRAM with a 28 nm CMOS technology, and the results show that the circuits are not only full featured and flexible for customization but also have a significant increase in the working frequency. At VDD = 0.9 V and T = 25 °C, the bi-directional search frequency is up to 775 MHz and 567 MHz, and the speeds for row and column Boolean logic reach 759 MHz and 683 MHz.