This study explores the impact of oxygen vacancy defects on elevated-metal metal-oxide (EMMO) IGZO TFTs under positive bias stress (PBS) using TCAD and DFT simulation. Findings reveal that oxygen vacancies accumulating at the channel/passivation layer interface and within the channel under PBS lead to negative threshold voltage shifts and reduced mobility. Additionally, higher tail state densities contribute to a positive Vth shift. These results provide important insights into the defect-related reliability of EMMO IGZO TFTs, guiding the design of more reliable devices.

Three-dimensional charge-trapping (CT) NAND flash memory has attracted extensive attention owing to its unique merits, including huge storage capacities, large memory densities, and low bit cost. The reliability property is becoming an important factor for NAND flash memory with multi-level-cell (MLC) modes like triple-level-cell (TLC) or quad-level-cell (QLC), which is seriously affected by the intervals between program (P) and erase (E) operations during P/E cycles. In this work, the impacts of the intervals between P&E cycling under different temperatures and P/E cycles were systematically characterized. The results are further analyzed in terms of program disturb (PD), read disturb (RD), and data retention (DR). It was found that fail bit counts (FBCs) during the high temperature (HT) PD process are much smaller than those of the room temperature (RT) PD process. Moreover, upshift error and downshift error dominate the HT PD and RT PD processes, respectively. To improve the memory reliability of 3D CT TLC NAND, different intervals between P&E operations should be adopted considering the operating temperatures. These results could provide potential insights to optimize the lifetime of NAND flash-based memory systems.