Reservoir computing (RC) is a low-cost and temporary-signal friendly computational framework, whose hardware implementation is hindered by integrating huge amounts and various kinds of devices. Benefitted from the logic in memory (LIM) capability, the process compatible Hf _0.5 Zr _0.5 O ₂ (HZO)-based ferroelectric field-effect-transistor (FeFET) is a promising candidate for implementing artificial networks. In this letter, a fully FeFETs RC network is proposed. Multiple functions can be achieved in a single device owing to its intrinsic characteristics, and the richness of virtual nodes is largely enhanced through full-connection structures. Impressively, only 44 FeFETs are required to construct a compact RC network with 100 ns operating speed and high accuracy in classification tasks. This paves the way to develop the high energy-efficiency FeFET RC networks.

3-D NAND flash memory has been attracting much attention owing to its ultrahigh storage density and low bit cost, and it has been widely applied in data centers and mobiles. 3-D triple-level-cell (TLC) NAND flash memory can achieve much larger storage capacity by storing 3 bits in each cell. However, the data reliability issues induced by data retention (DR) and read disturb (RD) greatly limit 3-D TLC NAND applications in hot data storage where the stored data are frequently accessed and RD is more serious. In this article, we first systematically study the retention correlated RD (RCRD) errors in 3-D charge trap (CT) TLC NAND flash memory under various conditions. Error characteristics and underlying mechanisms much different from 2-D NAND flash memory are observed: 1) for RCRD with short retention-after data program, error bits increase due to the negative-shift of program states and 2) for RCRD with long retention-after retention 12 h, error bits can be partially recovered on the contrary due to the charge compensation. We propose schemes of precharge the storage layer (PCSL) and thermally stabilize the storage layer (TSSL) to improve the reliability of 3-D NAND flash memory. By using these two methods, experimental results show that raw bit error rates (RBERs) can be significantly reduced by 30% and 20%, respectively.

Low-thermal-budget processing is strongly required to implement ferroelectric Hf _0.5 Zr _0.5 O ₂ (HZO) thin films to the back end of line (BEOL) of CMOS technologies. In this work, the O ₃ oxidation approach is used to form an interface oxidation layer between TiN and the following deposited HZO, achieving robust ferroelectricity under extremely low annealing temperatures. It is shown that, after rapid thermal annealing (RTA) at 350 °C (300 °C ), the maximum double remanent polarization (2 P_r ) could reach 42.6μC/cm ² (13.3μC/cm ² ) with more than 10 ⁸ field-cycling endurance. The formation of the TiO ₂ layer at the interface of HZO/TiN supplies greater tensile stress, which is responsible for the low-RTA-temperature ferroelectricity with an optimum oxidation time of 40s. The proposed TiN surface oxidation method facilitates the BEOL compatibility and provides feasible avenues to high-performance ferroelectric HZO thin films.

To achieve deep insights into the polarization switching kinetics in ferroelectric $\text{Hf}0.5\text{Zr}0.5\mathrm{O}_{2}$ (HZO), the intrinsic switching characteristics are measured accurately by using a novel pulse sequence to eliminate the charge trapping, polarization unsaturation and imprint effects. By NLS fittings, the average switching time and the concentration of pinning sites are extracted, with main focus on their dependences on the external electric field, the electrode size $l$ and the temperature $T$ . Although the average switching time shows weak dependence on $T,$ , it decreases sharply with $l$ scaling and sub-ns switching behavior is predicted at $l\leq 3.89\mu \mathrm{m}$ . More importantly, our observations intensely imply that a transition happens from NLS to KAI model when $T$ is below 161K or $l$ is approaching the grain size (10~30nm). This surprised but reasonable transition indicates that, as scaling the ferroelectric memory size or for operations under cryogenic temperatures, HZO ferroelectrics can switch much faster and more uniform.

Seed layer engineering in ferroelectric (FE) Hf0.5Zr0.5O2 (HZO) film has been investigated systematically in this work. Among four kinds of seed layers (ZrO2, HfO2, Al2O3, and TiO2), the HZO capacitor with TiO2 seed layer achieves preferable performance (larger Pr, smaller Ec, and nearly wakeup-free). It is considered that the suppression of interfacial defects by seed layers could be a key for wakeup-free achievement. For further understanding, with reliability characterizations and theoretical calculations, it is found that defects (oxygen vacancy $\text{V}_{\text {O}}^{+}$ ) generation at the TiN/HZO interface and their migration into inner film could be dominant reasons for the leakage and Pr degradation in cycling, while $\text{V}_{\text {O}}^{+}$ at the TiO2/TiN interface can attribute to the imprint effect. Thereby, a novel asymmetric stress field cycling (ASFC) scheme is proposed to suppress Pr fatigue by keeping defects at one-side interface rather than migrating into the inner film.