Resistive switching (RS) memory devices are gaining recognition as data storage devices due to the significant interest in their switching material, Halide perovskite (HP). The electrical characteristics include hysteresis in its current–voltage (I–V) relationship. It can be attributed to the production and migration of defects. This property allows HPs to be used as RS materials in memory devices. However, 3D HPs are vulnerable to moisture and the surrounding environment, making their devices more susceptible to deterioration. The potential of two-dimensional (2D)/quasi-2D HPs for optoelectronic applications has been recognized, making them a viable alternative to address current restrictions. Two-dimensional/quasi-2D HPs are created by including extended organic cations into the ABX₃ frameworks. By adjusting the number of HP layers, it is possible to control the optoelectronic properties to achieve specific features for certain applications. This article presents an overview of 2D/quasi-2D HPs, including their structures, binding energies, and charge transport, compared to 3D HPs. Next, we discuss the operational principles, RS modes (bipolar and unipolar switching), in RS memory devices. Finally, there have been notable and recent breakthroughs in developing RS memory systems using 2D/quasi-2D HPs.

Interpolation is used to approximate the timing parameters of logic cells not specified in timing tables. Bilinear interpolation has been taken for granted in the industry, but the error increases as the nonlinearity of the timing parameters increases. In this article, we propose machine learning (ML)-based interpolation to obtain more accurate timing parameters. Recurrent convolutional neural network (R-CNN) is employed and various ranges of table entries form a sequence of input data, in which the recurrent network allows them to influence the interpolation. In addition, variational autoencoder (VAE) is used to capture the distribution feature of the table. ML interpolation is parallelized in GPU to minimize the runtime overhead from numerous arithmetic operations. Experimental results demonstrate that ML interpolation reduces timing parameter error by 19.7% and path delay error by 3.4% compared to bilinear interpolation at the cost of 13% runtime overhead.

Power distribution network (PDN) requires more routing resources as wire resistance increases with technology scaling but IR drop constraint does not scale. We address post-placement PDN synthesis for mixed macro blocks and standard cells. Macro blocks already have partial PDN, while standard cells do not. So the design, which has been placed, is divided into a number of partitions: each macro block in its own partition, and standard cell area into a number of partitions. Multi-layer PDN synthesis is performed in each partition one by one; the goal of this problem is to insert minimum number of metal straps (in irregular pitches) while IR drop and electromigration (EM) constraints are respected. This is formulated as mixed integer quadratically constrained programming (MIQCP) and a heuristic algorithm is proposed for practical application. Experimental results with some test circuits indicate that the proposed approach achieves on average of 26% reduction in PDN straps, which helps reduce congestion overflow of signal routing by 15%, compared to popular approach in which PDN straps are located in regular pitch period.

Airgap technology enables air to be introduced in inter-metal dielectric (IMD). Airgap between certain wires reduces coupling capacitance due to the reduced permittivity; this can be utilized to decrease circuit delay. We propose an integrated approach of airgap insertion with the goal of circuit timing optimization. It consists of three sub-problems. We first select the layers that employ airgap, called airgap layers, that maximize total negative slack (TNS) improvement; this yields TNS improvement of 7% to 15% and worst negative slack (WNS) improvement of 2% to 8%, compared to a simple assumption of airgap layers. Second, we reassign the layers of wires such that more wires on critical paths can be placed in airgap layers. This is formulated as integer linear programming (ILP), and a more practical heuristic algorithm is also proposed. It provides an additional 17% TNS improvement and 6% WNS improvement. Finally, we perform airgap insertion through ILP formulation, where a number of design rules are modeled with linear constraints. To reduce the heavy runtime of ILP, a layout partitioning technique is also applied. It implements a feasible airgap mask in a manageable time where the amount of inserted airgap is close to the optimal solution.

Decoupling capacitor (decap) cells are inserted near function cells of high switching activities so that their IR-drop can be suppressed. Decaps become more complex these days while a number of metal layers are used for internal connection, thereby starting to manifest themselves as routing blockage. Postplacement decap insertion with both IR-drop violations and routing design rule violations (DRVs) being taken into account is addressed for the first time. Local cell relocation is performed to reduce the number of decaps in the actual decap insertion step. U-Net integrated with a graph convolutional network (GCN) is introduced to predict the DRV probability, which drives decap insertion. The problem of decap insertion is then formulated as mixed integer quadratically constrained programming (MIQCP) and a heuristic algorithm is presented for practical application. Experiments with a few test circuits demonstrate that the increase in routing DRV is reduced by 26% on average with no IR-drop violations, compared to conventional methods that do not explicitly consider DRVs. This brings a 60% reduction in routing runtime and a 33% improvement in total negative slack (TNS).