As solar radiation is the most plentiful energy source on earth, thermoelectric energy harvesting emerges as an interesting solution for the Internet of Things (IoTs) in outdoor applications, particularly using semiconductor thermoelectric generators (TEGs) to power IoT devices. However, when a TEG is under solar radiation, the temperature gradient through TEG is minor, meaning that the TEG is useless. A method to keep a significant temperature gradient on a TEG is by using a solar absorber on one side for heating and a heat sink on the other side. In this paper, a compact TEG-based energy harvester that features a solar absorber based on a new class of solid matter, the so-called quasicrystal (QC), is presented. In addition, a water-cooled heat sink to improve the temperature gradient on the TEG is also proposed. The harvester is connected to a power management circuit that can provide an output voltage of 3 V and store up to 1.38 J in a supercapacitor per day. An experimental evaluation was carried out to compare the performance of the proposed QC-based harvester with another similar harvester but with a solar absorber based on conventional black paint. As a result, the QC-based harvester achieved 28.6% more efficient energy generation and achieved full charge of a supercapacitor around two hours earlier. At last, a study on how much the harvested energy can supply power to a sensor node for Smart agriculture during a day while considering a trade-off between the maximum number of measurements and the maximum number of transmission per day is presented.

With heterogeneous computing on the rise, executing programs efficiently on different devices from a single source code has become increasingly important. OpenCL, having a bulk-synchronous programming model, has been proposed as a framework for writing such performance-portable programs. Execution order of work-items in a program is unconstrained except at barrier synchronization events, giving some freedom to an implementation when scheduling work-items between synchronization points. Many OpenCL (and CUDA) compilers have been designed for targeting multicore CPU architectures. However, scheduling work-items in prior work has been done with primary focus on correctness and vectorization. To the best of our knowledge, no existing implementations consider the impact of work-item scheduling on data locality. We propose an OpenCL compiler that performs data-locality-centric work-item scheduling. By analyzing the memory addresses accessed in loops within a kernel, our technique can make better decisions on how to schedule work-items to construct better memory access patterns, thereby improving performance. Our approach achieves geomean speedups of 3.32× over AMD's and 1.71 × over Intel's implementations on Parboil and Rodinia benchmarks.

For the first time, low-k dielectric ALD-SiBN (atomic layer deposition) is successfully developed and applied on poly-Si/WSix gate as a spacer for reduction of parasitic capacitance between the cells. ALD-SiBN deposition is performed at 630/spl deg/C using dichlorosilane (SiH/sub 2/Cl/sub 2/-DCS), boron-trichloride (BCl/sub 3/) and ammonia (NH/sub 3/) as precursors. Compared with the conventional silicon nitride, ALD-SiBN exhibits similar film properties at lower dielectric constant. ALD-SiBN layer is deposited on poly-Si/WSix stack gate in 90nm NAND flash device. A significant reduction (>15%) of the floating-gate coupling voltage is achieved by employing SiBN compared with SiN spacer. In addition, excellent data retention characteristics (@HTS) is identified by applying low-k dielectric SiBN layer as a spacer on 90nm NAND flash device.

Advanced energy conversion and storage systems have attracted much attention in recent decades due to the increasing demand for energy and the environmental impacts of non-sustainable energy resources

The precise evaluation of real-world thermoelectric cooling (TEC) performance is vital for both the development of TEC devices and the rational design of TEC materials. Due to the relatively limited temperature difference (ΔT) that a single-stage TEC can achieve, the classical analytical formulae for thermoelectric cooling are commonly used with averaged material properties in the cooling performance evaluation. Nevertheless, this could cause remarkable errors in evaluations of the cooling power, even under a ΔT as low as 10 K. In this work, a cumulative model for thermoelectric cooling is proposed to evaluate the maximum coefficient of performance (COP) as well as the maximum cooling power of a TEC device under finite temperature differences, with the temperature dependence of material properties being fully considered. The inherent deficiencies in predicting the maximum cooling power by both the classical formulae and the original cumulative model are identified, and effective refinements are implemented to reduce the prediction error. Eight thermoelectric materials with state-of-the-art ZT values near room temperature are assessed for electronics cooling scenarios within a cold side temperature (Tc) range of 300-350 K. In comparison to the classical formulae, the proposed model predicts the maximum COP with comparably satisfying accuracies (±2%), while significantly improves the prediction accuracy of the maximum cooling power from approximately ±30% to within ±5% over a ΔT range of 10-70 K. This work fills the gap between thermoelectric material properties and device-level cooling performance, and is beneficial to the development and application of thermoelectric conversion technology for cooling purposes.