Matthias Jung

Prof. Dr. Matthias Jung

Fraunhofer-Platz 1, Raum C1.24, 67663 Kaiserslautern, Germany
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Academic Career Length

30Years (1997-Present)

(Calculated once Scilit publication data is synced: current year − year of first publication + 1)

Representative Publications

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1 January 2015 in IPSJ Transactions on System and LSI Design Methodology
Verified
Journal Article
Closed access
MJMatthias Jung
Matthias Jung
CWChristian Weis
Christian Weis
NWNorbert Wehn
Norbert Wehn
5 October 2015
Verified
Conference Paper
Open access
PDF file
MJMatthias Jung
Matthias Jung
ÉZÉder Zulian
Éder Zulian
DMDeepak M. Mathew
Deepak M. Mathew
MHMatthias Herrmann
Matthias Herrmann
CBChristian Brugger
Christian Brugger
NWNorbert Wehn
Norbert Wehn
Dynamic Random Access Memories (DRAM) have a big impact on performance and contribute significantly to the total power consumption in systems ranging from mobile devices to servers. Up to half of the power consumption of future high density DRAM devices will be caused by refresh commands. Moreover, not only the refresh rate does depend on the device capacity, but it strongly depends on the temperature as well. In case of 3D integration of MPSoCs with Wide I/O DRAMs the power density and thermal dissipation are increased dramatically. Hence, in 3D-DRAM even more DRAM refresh operations are required. To master these challenges, clever DRAM refresh strategies are mandatory either on hardware or on software level using new or already available infrastructures and implementations, such as Partial Array Self Refresh (PASR) or Temperature Compensated Self Refresh (TCSR). In this paper, we show that for dedicated applications refresh can be disabled completely without or with negligible impact on the application performance. This is possible if it is assured that either the lifetime of the data is shorter than the currently required DRAM refresh period or if the application can tolerate bit errors to some degree in a given time window.
5 June 2016
Verified
Conference Paper
Open access
MJMatthias Jung
Matthias Jung
DMDeepak M. Mathew
Deepak M. Mathew
CWChristian Weis
Christian Weis
NWNorbert Wehn
Norbert Wehn
1 June 1997 in Physical Review A
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Journal Article
Closed access
PDF file
UAU. Arp
U. Arp
TLT. LeBrun
T. LeBrun
SSS. H. Southworth
S. H. Southworth
MMM. A. MacDonald
M. A. MacDonald
MJMatthias Jung
Matthias Jung
Argon L2,3-M2,3M2,3 Auger-electron spectra were measured in coincidence with Kα fluorescent x rays in studies of K-shell vacancy decays at several photon energies above the K threshold and on the 1s→4p resonance. The complex spectra recorded by conventional electron spectroscopy are greatly simplified when recorded in coincidence with fluorescent x rays, allowing a more detailed analysis of the vacancy cascade process. The resulting coincidence spectra are compared with Hartree-Fock calculations, which include shake-up transitions in the resonant case. Small energy shifts of the coincident electron spectra are attributed to postcollision interaction with 1s photoelectrons.
17 May 2017 in IEEE Design & Test
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Journal Article
Closed access
MJMatthias Jung
Matthias Jung
DMDeepak M. Mathew
Deepak M. Mathew
CRCarl C. Rheinlander
Carl C. Rheinlander
CWChristian Weis
Christian Weis
NWNorbert Wehn
Norbert Wehn
The authors explore the intrinsic trade-off in a DRAM between the power consumption (due to refresh) and the reliability. Their unique platform allows tailoring to the design constraints depending on whether power consumption, performance or reliability has the highest design priority.
12 March 2022 in International Journal of Parallel Programming
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Journal Article
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LSLukas Steiner
Lukas Steiner
MJMatthias Jung
Matthias Jung
FPFelipe S. Prado
Felipe S. Prado
KBKirill Bykov
Kirill Bykov
NWNorbert Wehn
Norbert Wehn
The simulation of Dynamic Random Access Memories (DRAMs) on system level requires highly accurate models due to their complex timing and power behavior. However, conventional cycle-accurate DRAM subsystem models often become a bottleneck for the overall simulation speed. A promising alternative are simulators based on Transaction Level Modeling, which can be fast and accurate at the same time. In this paper we present DRAMSys4.0, which is, to the best of our knowledge, the fastest and most extensive open-source cycle-accurate DRAM simulation framework. DRAMSys4.0 includes a novel software architecture that enables a fast adaption to different hardware controller implementations and new JEDEC standards. In addition, it already supports the latest standards DDR5 and LPDDR5. We explain how to apply optimization techniques for an increased simulation speed while maintaining full temporal accuracy. Furthermore, we demonstrate the simulator’s accuracy and analysis tools with two application examples. Finally, we provide a detailed investigation and comparison of the most prominent cycle-accurate open-source DRAM simulators with regard to their supported features, analysis capabilities and simulation speed.