The simulation of Dynamic Random Access Memories (DRAMs) on system level requires highly accurate models due to their complex timing and power behavior. However, conventional cycle-accurate DRAM subsystem models often become a bottleneck for the overall simulation speed. A promising alternative are simulators based on Transaction Level Modeling, which can be fast and accurate at the same time. In this paper we present DRAMSys4.0, which is, to the best of our knowledge, the fastest and most extensive open-source cycle-accurate DRAM simulation framework. DRAMSys4.0 includes a novel software architecture that enables a fast adaption to different hardware controller implementations and new JEDEC standards. In addition, it already supports the latest standards DDR5 and LPDDR5. We explain how to apply optimization techniques for an increased simulation speed while maintaining full temporal accuracy. Furthermore, we demonstrate the simulator’s accuracy and analysis tools with two application examples. Finally, we provide a detailed investigation and comparison of the most prominent cycle-accurate open-source DRAM simulators with regard to their supported features, analysis capabilities and simulation speed.

Emerging memory-intensive applications require a paradigm shift from processor-centric to memory-centric computing. The performance of state-of-the-art computing systems and accelerators designed for such applications is not limited by the processing speed but rather by the limited DRAM bandwidth and long DRAM latencies. Although, the interface frequency of new commodity DRAM memories is constantly increasing to achieve a higher peak bandwidth, this bandwidth cannot be fully utilized due to long internal latencies. Page-misses (i.e. change of active row) are one of the key contributors to long access latencies that result in a low bandwidth utilization. In this paper, we propose a novel DRAM sub-array level architecture referred to as Dual-Sense-Amplifier (DSA) that masks the page-miss latency by allowing individual sub-arrays or banks to flexibly open two rows concurrently. Additionally, the DSA architecture design aim to be fully compatible with any type of commodity DRAM architecture (e.g. HBM, GDDR, etc.) and to retain most of its circuit designs. The area overhead of DSA for an 8 Gb device is 9.6% compared to a commodity DRAM device. On average, a DSA 8 Gb device improves the bandwidth utilization by 17.53% and reduces the average response latency by 31.59 ns compared to commodity DRAM devices operated at 800 MHz. Moreover, we demonstrate that the energy consumption overhead of a DSA DRAM in comparison to a commodity DRAM is negligible.