For years, researchers have been recognizing patterns in gait for purposes of medical diagnostics, rehabilitation, and biometrics. A method for observing gait is to measure ground reaction forces (GRFs) between the foot and solid plate with tension sensors. The presented dataset consists of 13,702 measurements of bipedal GRFs of one step of normal gait of 324 students wearing shoes of various types. Each measurement includes raw digital signals of two force plates. A signal comprises stance-related samples but also preceding and following ones, in which one can observe noise, interferences, and artifacts caused by imperfections of devices and walkway. Such real-world time series can be used to study methods for detecting foot-strike and foot-off events, and for coping with artifacts. For user convenience, processed data are also available, which describe only the stance phase of gait and form ready-to-use patterns suitable for experiments in GRF-based recognition of persons and footwear, and for generating synthetic GRF waveforms. The dataset is accompanied by Matlab and Python programs for organizing and validating data.

A lifting-based structure for quaternion multipliers with unit-magnitude constant coefficients is proposed, whose development was inspired by the well-known implementation of a plane rotation (complex multiplication with a unit-magnitude coefficient) using three shears each of which corresponds to one real multiplication and addition. Our solution is mainly aimed at implementing quaternion transforms as dedicated multiplierless digital circuits. Compared to alternative schemes obtained using the most known general-purpose lifting factorizations, it needs 1/3-1/5 less lifting steps. On general-purpose hardware, it allows for saving 14% operations at the price of representing the hypercomplex coefficient indirectly using six, instead of four, real numbers.

Novel 4D CORDIC algorithms and hardware architecture for multiplying quaternions are presented, aimed at constant-coefficient multipliers. In our solution, microrotations are multiplications by hypercomplex numbers with only one non-zero imaginary part. Such transformations can be described using sparse matrices and implemented using less hardware resources than the iteration of the known quaternion CORDIC algorithm. Chip area can be saved because sparse microrotations can be computed using a permutation network and two-operand adders, without four-operand additions, which are necessary in the known solution. The obtainable area savings depend on the implementation technology and the architectures of adders and bit shifters but can be as large as 45 and 25 percent for ASIC and FPGA circuits, respectively. The circuitry simplifications come at the cost of slowing down computations: our approach improves the area-delay product, and a single sparse iteration can be executed up to 15 percent faster than the conventional one, but more microrotations are usually necessary to achieve the required accuracy. On the other hand, a sparse 4D iteration can be identified with microrotations of two 2D CORDICs which work in parallel. This makes convergence analysis easier than in the previous 4D solution, as it is sufficient to consider only two dimensions.

A family of multiplierless transforms is presented that approximate the eight‐point type‐II discrete cosine transform (DCT) as accurately as the state‐of‐the‐art scaled DCT schemes, but having 14–17% shorter critical paths (1/6 or 1/7 less adders). Compared to the existing solutions that use the coordinate rotation digital computer (CORDIC) algorithm, the advantage of higher throughput is accompanied by saving additions. Only some lifting‐based BinDCT schemes require less adders in total, in spite of longer critical paths. The transforms have been derived from the fast Loeffler's algorithm by replacing the rotation stage with unfolded CORDIC iterations, which have been arranged so that two rotation approximations use the same scaling. This is equivalent to imposing structural orthogonality (losslessness) on a system, from which the scaling can then be extracted so as to shorten the critical path. Supporting ideas are a notation for more conveniently describing CORDIC circuits, and an angle conversion that allows rotations to be approximated using an extended set of CORDIC circuits. The research results have been validated by field programmable gate array‐based hardware design experiments and by usability tests based on a software JPEG codec.

A novel approach to the design and implementation of four-channel paraunitary filter banks is presented. It utilizes hypercomplex number theory, which has not yet been employed in these areas. Namely, quaternion multipliers are presented as alternative paraunitary building blocks, which can be regarded as generalizations of Givens (planar) rotations. The corresponding quaternionic lattice structures maintain losslessness regardless of coefficient quantization and can be viewed as extensions of the classic two-band lattice developed by Vaidyanathan and Hoang. Moreover, the proposed approach enables a straightforward expression of the one-regularity conditions. They are stated in terms of the lattice coefficients, and thus can be easily satisfied even in finite-precision arithmetic.