With the immense increase in the processing data during the scaling down of semiconductor devices by Moore’s Law, it is in urgent need to use data analytics to meet the state of the art performance in both manufacturing and device compact modeling. In particular, managing the fabrication cost and promptly providing compact device models, especially for new or emerging devices, is challenging. To ease out these issues, we propose a unified, general-purpose, process-aware machine learning (ML) based compact model (CM) for resistive random-access memory (RRAM), and the same methodology can be used for any memory devices with hysteresis. A long short-term memory (LSTM) ML model is used to fit the RRAM current-voltage (I-V) characteristics. The memorizing capability of LSTM ensures one model can fit both RRAM low resistance state (LRS) and high resistance state (HRS). The fitted dataset is based on the fabricated RRAM samples using TaN/HfO ₂ /Pt/Ti/SiO ₂ /Si structure. The resultant fitting error is 0.0096 in sinusoidal wave input voltage and 0.0148 in random walk voltage sequences. In the process-aware demonstration, we use post-oxide annealing dataset from 300°C to 500°C. The root mean squared error (RMSE) in the process-aware RRAM compact model is 0.0028. Thus, the LSTM-based CM has the potential to compete with the conventional compact device models in terms of shorter developing time, better fitting capability in emerging devices and a large number of devices, easily incorporated process-aware models, and one unified model accounting for LRS and HRS ensuring differentiability. We propose that the LSTM based memory CM can be useful in intelligent manufacturing, process tuning, and simulation program with integrated circuit emphasis (SPICE) modeling in circuit simulation.

Machine learning (ML)-based compact model (CM) provide an alternative way in contrast to physics-based CMs. The advantages of ML CMs include the process-aware capability, expandability, improved behavioral model for a circuit block, and usability for emerging devices. On the other hand, while ML is on the rise, device physics can provide many guidelines in constructing ML CMs. Here, we propose a physics architecture in ML CMs for resistive random access memory (RRAM). The results show that the physics-assisted architecture enables simpler ML models in reference to our previous work of long short-term memory (LSTM)-based RRAM CMs. We found that the discrete state variable with classification is the best model to describe the RRAM set/reset scenario in multistep prediction problems. For the discrete and continuous state variables, the root mean square error (RMSE) on test data is 0.000125 and 0.000119, respectively. In addition, we demonstrate that the transient behavior of set/reset changes can be easily incorporated into the proposed model. Finally, the Verilog-A and HSPICE on a 1T1R cell have also been shown to prove the model feasibility. We suggest that the uniform framework with hybridization in physics and ML should be the most efficient way in future compact device modeling. The code is available at https://github.com/albertlin11/RRAMunif .

Artificial neural networks (ANN) and multilayer perceptrons (MLP) have proved to be efficient in terms of designing highly accurate semiconductor device compact models (CM). Their ability to update their weight and biases through the backpropagation method makes them highly useful in learning the task. To improve the learning, MLP usually requires large networks and thus a large number of model parameters, which significantly increases the simulation time in circuit simulation. Hence, optimizing the network architecture and topology is always a tedious yet important task. In this work, we tune the network topology using neuro-evolution (NE) to develop semiconductor device CMs. With input and output layers defined, we have allowed a genetic algorithm (GA), a gradient-free algorithm, to tune the network architecture in combination with Adam, a gradient-based backpropagation algorithm, for the network weight and bias optimization. In addition, we implemented the MLP model using a similar number of parameters as the baseline for comparison. It is observed that in most of the cases, the NE models exhibit a lower root mean square error (RMSE) and require fewer training epochs compared to the MLP baseline models. For instance, for patience number 100 with different number of model parameters, the RMSE for test dataset using NE and MLP in unit of log(ampere) are 0.1461, 0.0985, 0.1274, 0.0971, 0.0705, and 0.2254, 0.1423, 0.1429, 0.1425, 0.1391, respectively, for the 28nm technology node at foundry. The code is available at Github.

It is always highly desired to have a well-defined relationship between the chemistry in semiconductor processing and the device characteristics. With the shrinkage of technology nodes in the semiconductors roadmap, it becomes more complicated to understand the relation between the device electrical characteristics and the process parameters such as oxidation and wafer cleaning procedures. In this work, we use a novel machine learning approach, i.e., physics-assisted multitask and transfer learning, to construct a relationship between the process conditions and the device capacitance voltage curves. While conventional semiconductor processes and device modeling are based on a physical model, recently, the machine learning-based approach or hybrid approaches have drawn significant attention. In general, a huge amount of data is required to train a machine learning model. Since producing data in the semiconductor industry is not an easy task, physics-assisted artificial intelligence has become an obvious choice to resolve these issues. The predicted C–V uses the hybridization of physics, and machine learning provides improvement while the coefficient of determination (R²) is 0.9442 for semisupervised multitask learning (SS-MTL) and 0.9253 for transfer learning (TL), referenced to 0.6108 in the pure machine learning model using multilayer perceptrons. The machine learning architecture used in this work is capable of handling data sparsity and promotes the usage of advanced algorithms to model the relationship between complex chemical reactions in semiconductor manufacturing and actual device characteristics. The code is available at https://github.com/albertlin11/moscapssmtl.

With the shrinking of the IC technology node, optical proximity effects (OPC) and etch proximity effects (EPC) are the two major tasks in advanced photolithography patterning. Machine learning has emerged in OPC/EPC problems because conventional optical-solver-based OPC is time-consuming, and there is no physical model existing for EPC. In this work, we use dimensionality reduction (DR) algorithms to reduce the computation time of complex OPC/EPC problems while the prediction accuracy is maintained. Also, we implement a pure machine learning approach where the input masks are directly mapped to the output etched patterns. While one photolithographic mask can generate many experimental patterns at once, our pure ML-based approach can shorten the trial-and-error period in the photolithographic correction. Additionally, we demonstrate the automation in SEM images preprocessing using feature detection, and this facilitates intelligent manufacturing in semiconductor processing. The input vector dimensions are effectively reduced by two orders of magnitude while the observed mean squared error is not affected significantly. The computation runtime is reduced from 4804s of the baseline calculation to 10s-200s The MSE values changed from the baseline 0.037 to 0.037 for singular value decomposition (SVD), to 0.039 for independent component analysis (ICA), and to 0.035 for factor analysis (FA).

For high-power silicon carbide (SiC) devices, breakdown voltage analysis is an important parameter, especially for guard ring design. This work explores the implementation of machine learning on SiC guard ring parameters such as ion implanted dose and energy. In this work, the reinforcement learning method has been successfully implemented on the 1.7kV SiC guard ring device TCAD simulated data for the prediction of parameters. Our work has predicted the parameters successfully for the 2.5kV guard ring design. For training, proximal policy optimization (PPO) and advantage actor-critic (A2C) RL agents were deployed. The network architecture was kept at “auto” with 3 hidden layers of 128 neurons in each layer. Our method is practically feasible and easily implemented as compared to other works, and has been shown in this paper. By using the limited design parameters of the 1.7kV guard ring device, the trained agent has successfully predicted the design parameters for the 2.5kV guard ring device, which has been confirmed using TCAD simulations. This work is more accurate, practical, and result-oriented, and we believe that this can significantly minimize the computational cost as compared to the standalone TCAD simulations. Also, this implementation of ML on TCAD data can substantially accelerate the design exploration for the power devices and ultimately lower product-to-market time.