Chemical mechanical polishing (CMP) is a well-known technology that can produce surfaces with outstanding global planarization without subsurface damage. A good CMP process for Silicon Carbide (SiC) requires a balanced interaction between SiC surface oxidation and the oxide layer removal. The oxidants in the CMP slurry control the surface oxidation efficiency, while the polishing mechanical force comes from the abrasive particles in the CMP slurry and the pad asperity, which is attributed to the unique pad structure and diamond conditioning. To date, to obtain a high-quality as-CMP SiC wafer, the material removal rate (MRR) of SiC is only a few micrometers per hour, which leads to significantly high operation costs. In comparison, conventional Si CMP has the MRR of a few micrometers per minute. To increase the MRR, improving the oxidation efficiency of SiC is essential. The higher oxidation efficiency enables the higher mechanical forces, leading to a higher MRR with better surface quality. However, the disparity on the Si-face and C-face surfaces of 4H- or 6H-SiC wafers greatly increases the CMP design complexity. On the other hand, integrating hybrid energies into the CMP system has proven to be an effective approach to enhance oxidation efficiency. In this review paper, the SiC wafering steps and their purposes are discussed. A comparison among the three configurations of SiC CMP currently used in the industry is made. Moreover, recent advances in CMP and hybrid CMP technologies, such as Tribo-CMP, electro-CMP (ECMP), Fenton-ECMP, ultrasonic-ECMP, photocatalytic CMP (PCMP), sulfate-PCMP, gas-PCMP and Fenton-PCMP are reviewed, with emphasis on their oxidation behaviors and polishing performance. Finally, we raise the importance of post-CMP cleaning and make a summary of the various SiC CMP technologies discussed in this work.

Gallium nitride (GaN) possesses remarkable characteristics such as a wide bandgap, high critical electric field, robust antiradiation properties, and a high saturation velocity for high-power devices. These attributes position GaN as a pivotal material for the development of power devices. Among the various GaN-based devices, vertical GaN MOSFETs stand out for their numerous advantages over their silicon MOSFET counterparts. These advantages encompass high-power device applications. This review provides a concise overview of their significance and explores their distinctive architectures. Additionally, it delves into the advantages of vertical GaN MOSFETs and highlights their recent advancements. In conclusion, the review addresses methods to enhance the breakdown voltage of vertical GaN devices. This comprehensive perspective underscores the pivotal role of vertical GaN MOSFETs in the realm of power electronics and their continual progress.

Silicon carbide (SiC) power mosfets provide superior device characteristics, increasing their demand in high-power systems. However, the advantages of SiC also cause switching challenges, including overshoot, oscillation, and electromagnetic interference (EMI). This article introduces a universal active gate driver (AGD) IC to mitigate these issues and achieve a better tradeoff between overshoot and switching losses (E_LOSS). The AGD IC integrates a gate-sensing technique, eliminating the need for external sensing components, and dynamically adjusts driving strength during switching operations, effectively suppressing overshoot, oscillation, and EMI. Moreover, the proposed driver can automatically drive different SiC power devices, enhancing its utility flexibility. Validation using the 0.18-μm BCD process demonstrates the functionality of the proposed AGD, achieving notable reductions of 48.7% and 18.8% in turn-on and turn-off switching losses, respectively, compared to conventional gate drivers under similar current and voltage overshoot. These findings confirm the advancements of the proposed AGD in improving the efficiency and reliability of SiC-based power management systems.

In this study, we explore the stability of third-quadrant characteristics in planar SiC power MOSFETs under high drain bias above the avalanche breakdown condition. By using experimental measurements and TCAD simulations, we analyze the mechanisms responsible for the positive shift of reverse turn-on voltage ( ${V}_{\text {rev}, \text {on}}$ ) during the third-quadrant operation. When the drain bias is increased from 1500 to 1620 V, obvious negative shifts in threshold voltage ( ${V}_{\text {TH}}$ ) and positive shifts in ${V}_{\text {rev}, \text {on}}$ are observed. The TCAD simulations attribute these shifts to the impact ionization caused by the high electric field inside the p-well regions. Furthermore, with the inclusion of positive fixed charges as the hole traps in the gate oxide near the SiO2/SiC interface, the simulation results show positive shifts of ${V}_{\text {rev}, \text {on}}$ consistent with the experimental results. These findings suggest that hole trapping caused by high drain bias above the avalanche breakdown condition can affect the stability of third-quadrant operation in planar SiC power MOSFETs.

For high-power silicon carbide (SiC) devices, breakdown voltage analysis is an important parameter, especially for guard ring design. This work explores the implementation of machine learning on SiC guard ring parameters such as ion implanted dose and energy. In this work, the reinforcement learning method has been successfully implemented on the 1.7kV SiC guard ring device TCAD simulated data for the prediction of parameters. Our work has predicted the parameters successfully for the 2.5kV guard ring design. For training, proximal policy optimization (PPO) and advantage actor-critic (A2C) RL agents were deployed. The network architecture was kept at “auto” with 3 hidden layers of 128 neurons in each layer. Our method is practically feasible and easily implemented as compared to other works, and has been shown in this paper. By using the limited design parameters of the 1.7kV guard ring device, the trained agent has successfully predicted the design parameters for the 2.5kV guard ring device, which has been confirmed using TCAD simulations. This work is more accurate, practical, and result-oriented, and we believe that this can significantly minimize the computational cost as compared to the standalone TCAD simulations. Also, this implementation of ML on TCAD data can substantially accelerate the design exploration for the power devices and ultimately lower product-to-market time.

The integration of thick homoepitaxial layers on silicon carbide (SiC) substrates is critical for enabling high-voltage power devices, yet it remains challenged by substrate surface quality and wafer geometry evolution. This study investigates the relationship between substrate preparation—particularly chemical mechanical planarization (CMP)—and the impact on wafer bow, total thickness variation (TTV), local thickness variation (LTV), and defect propagation during epitaxial growth. Seven 150 mm, 4° off-axis, prime-grade 4H-SiC substrates from a single ingot were processed under high-volume manufacturing (HVM) conditions and grown with epitaxial layers ranging from 12 μm to 100 μm. Metrology revealed a strong correlation between increasing epitaxial thickness and geometric deformation, especially beyond 31 μm. Despite initial surface scratches from CMP, hydrogen etching and buffer layer deposition significantly mitigated scratch propagation, as confirmed through defect mapping and SEM/FIB analysis. These findings provide a deeper understanding of the substrate-to-epitaxy integration process and offer pathways to improve manufacturability and yield in thick-epilayer SiC device fabrication.