In modern semiconductor manufacturing, optimizing plasma etching processes is key for advancing technology and achieving profitable production. In this study, we propose an efficient process flow to calibrate the etching mechanisms and optimize the etch profile by combining three-dimensional plasma simulations with machine learning (ML). Our proposed workflow speeds up the model calibration process and effectively addresses data scarcity issues by integrating extensive simulation data with TEM and other data sources. We have developed a three-dimensional Cl2/HBr/O2 plasma etching model for shallow trench isolation (STI), which is based on physical and chemical reaction mechanisms and external parameters consistent with actual production requirements, such as gas ratio, time duration, and chamber conditions. Machine learning is employed to tackle both forward and inverse problems. In the forward problem, the model predicts etching profiles under varying process conditions, with accuracy and similarity assessed using multiple criteria, including the structural similarity index (SSIM). Our approach achieves a notable reduction in prediction time, completing forecasts in 0.5 seconds compared to the 6500 CPU seconds required by TCAD. In the inverse problem, the model adjusts physical parameters to match observed results, improving its predictive accuracy. After model calibration, predictions are validated with wafer test outcomes, showing relative errors below 7%, thereby confirming the accuracy and robustness of the model parameters and the effectiveness of the entire process.

As the device dimensions continue to shrink, numerous challenges emerge, significantly impacting the design and fabrication of modern silicon-based integrated circuits (ICs). This work presents a comprehensive analysis of performance variations in metal-oxide semiconductor (MOS) devices of ICs. First, the primary sources of performance variations are explored, including process variations, material properties, device geometry, operating conditions et al. A detailed investigation into random dopant fluctuation, line edge roughness /line width roughness, and work function variation is conducted. Furthermore, the mechanisms causing these variations and their impacts on device parameters such as threshold voltage, mobility, and leakage current are discussed. More importantly, advanced modeling techniques and mitigation strategies are proposed, including optimized doping distributions, improved annealing techniques, the adoption of new device architectures, circuit-level design techniques et al. In addition, this review also highlights the importance of developing accurate models for predicting device performance variations and the ongoing research efforts to address the challenges posed by device scaling. By providing a comprehensive understanding of the sources, mechanisms, and mitigation techniques of performance variations in MOS devices, it aims to provide guideline for future research and development in silicon-based IC technology.

Optimizing LDMOS performance requires balancing breakdown voltage (BV) and specific on-resistance ( $\text {R}_{\text {on},\text {sp}}$ ) under silicon-limit constraints. Conventional technology computer-aided design (TCAD)-based device design is time-consuming and inefficient for large parameter spaces. This work presents a machine learning (ML)-assisted framework that combines initial and fine-tuned deep neural network (DNN) surrogate models with multi-objective particle swarm optimization (MOPSO). The fine-tuned DNN adapts to a non-overlapping extended design space using only a small dataset, while the two surrogates are selectively applied during MOPSO to evaluate candidate designs, enabling significantly faster design evaluation compared to TCAD. SHAP analysis reveals consistent feature importance that aligns with the underlying device physics. The framework constructs diverse Pareto-optimal fronts, offering a scalable solution for automated LDMOS optimization under complex performance trade-offs.

In this paper, we propose a lightweight lithography machine learning-based hotspot detection model that integrates the Squeeze-and-Excitation (SE) attention mechanism and the Efficient Channel Attention (ECA) mechanism. These mechanisms can adaptively adjust channel weights, significantly enhancing the model’s ability to extract relevant features of hotspots and non-hotspots through cross-channel interaction without dimensionality reduction. Our model extracts feature vectors through seven convolutional layers and four pooling layers, followed by three fully connected layers that map to the output, thereby simplifying the CNN network structure. Experimental results on our collected layout dataset and the ICCAD 2012 layout dataset demonstrate that our model is more lightweight. By evaluating overall accuracy, recall, and runtime, the comprehensive performance of our model is shown to exceed that of ConvNeXt, Swin transformer, and ResNet 50.

This study proposes a novel framework integrating long short-term memory (LSTM) networks with Bayesian optimization (BO) to address process–device co-optimization challenges in trench-gate metal–oxide–semiconductor field-effect transistor (MOSFET) manufacturing. Conventional TCAD simulations, while accurate, suffer from computational inefficiency in high-dimensional parameter spaces. To overcome this, an LSTM-based TCAD proxy model is developed, leveraging hierarchical temporal dependencies to predict electrical parameters (e.g., breakdown voltage, threshold voltage) with deviations below 3.5% compared to physical simulations. The model, validated on both N-type and P-type 20 V trench MOS devices, outperforms conventional RNN and GRU architectures, reducing average relative errors by 1.78% through its gated memory mechanism. A BO-driven inverse optimization methodology is further introduced to navigate trade-offs between conflicting objectives (e.g., minimizing on-resistance while maximizing breakdown voltage), achieving recipe predictions with a maximum deviation of 8.3% from experimental data. Validation via TCAD-simulated extrapolation tests and SEM metrology confirms the framework’s robustness under extended operating ranges (e.g., 0–40 V drain voltage) and dimensional tolerances within industrial specifications. The proposed approach establishes a scalable, data-driven paradigm for semiconductor manufacturing, effectively bridging TCAD simulations with production realities while minimizing empirical trial-and-error iterations.