In this paper, we propose a lightweight lithography machine learning-based hotspot detection model that integrates the Squeeze-and-Excitation (SE) attention mechanism and the Efficient Channel Attention (ECA) mechanism. These mechanisms can adaptively adjust channel weights, significantly enhancing the model’s ability to extract relevant features of hotspots and non-hotspots through cross-channel interaction without dimensionality reduction. Our model extracts feature vectors through seven convolutional layers and four pooling layers, followed by three fully connected layers that map to the output, thereby simplifying the CNN network structure. Experimental results on our collected layout dataset and the ICCAD 2012 layout dataset demonstrate that our model is more lightweight. By evaluating overall accuracy, recall, and runtime, the comprehensive performance of our model is shown to exceed that of ConvNeXt, Swin transformer, and ResNet 50.

For the past few decades, metal–oxide–semiconductor field-effect transistors (MOSFETs) have been the most important application in IC circuits. In certain circuit applications, the breakdown voltage and specific on-resistance serve as key electrical parameters. This article introduces a readily accessible approach to enhance the source–drain breakdown voltage (BVDS) of MOSFETs based on the Bipolar-CMOS-DMOS (BCD) platform without extra costs. By attentively refining the process steps and intricacies of the doping procedures, the breakdown voltages of NMOS and PMOS experienced increments of 3.4 V and 4.6 V, translating to enhancements of 31.5% and 50.3%. Parallel simulations offer insightful mechanistic explanations through simulation tools, facilitating superior outcomes. This initiative lays significant groundwork for the advancement of a comprehensive BCD process development framework.

With the rapid development of modern science and technology, the stability and reliability of electronic components become essential. Low-temperature drift resistors (LTDRs) are of importance owing to their excellent performance and stability in different temperature environments. LTDR technology is now widely used in the industrial field. This paper reviews the research status of LTDRs in order to provide reference for researchers and engineers in related fields. First, the basic principle of LTDRs is briefly discussed. A brief explanation of the mechanism behind low-temperature drift is illustrated. Second, the materials, types, and manufacturing processes of LTDRs are classified and discussed. The review ends with a brief conclusion concerning the challenges from mechanism to application and the future outlook.

In power systems, MOSFET devices used in industrial chips exhibit more pronounced degradation when subjected to intense electromagnetic pulses than in conventional environments. Conventional reliability testing methods, which fail to simulate dynamic electromagnetic environments, are unable to accurately assess the changes in device performance under electromagnetic interference. In this study, we employed a transmission line pulse generator to apply pulse stress to N-type MOSFET devices, systematically investigating the degradation mechanisms by varying pulse features such as pulse cycle, amplitude, rise/fall times, and intervals. The results indicate that changes in the electrical properties of the devices are primarily influenced by two types of charged traps. Under the conditions of low pulse cycles, the current response of the devices may even exceed that prior to stress application. The study further analyzed the competitive mechanisms of these different traps during the device degradation process. Additionally, by varying the test temperature to mimic industrial application scenarios, we analyzed the degradation behavior of the devices under multi-physics conditions.