An energy-efficient SoC with 32 b subthreshold RISC processor cores, 32 kB conventional cache memory, and 9T ultra-low voltage (ULV) SRAM based on a flexible and extensible architecture was fabricated on a 2.7 mm² test chip in 65 nm low power CMOS. The processor cores are based on a custom standard cell library that was designed using a multiobjective approach to optimize noise margins, switching energy, and propagation delay simultaneously. The cores operate over a supply voltage range from 200 mV (best samples) to 1.2 V with clock frequencies from 10 kHz to 94 MHz at room temperature. The lowest energy consumption per cycle of 9.94 pJ is observed at 325 mV and 133 kHz. A 2 kb ULV SRAM macro achieves minimum energy per operation at averages of 321 mV (0.030 σ/μ), 567 fJ (0.037 σ/μ), and 730 kHz (0.184 σ/μ), for equal number of 32 b read/write operations. The off-chip performance and power management subsystem provides dynamic voltage and frequency scaling (DVFS) combined with an adaptive supply voltage generation for dynamic PVT compensation.

MPSoCs with hierarchical communication infrastructures are promising architectures for low power embedded systems. Multiple CPU clusters are coupled using an Network-on-Chip (NoC). Our CoreVA-MPSoC targets streaming applications in embedded systems, like signal and video processing. In this work we introduce a tightly coupled shared data memory to each CPU cluster, which can be accessed by all CPUs of a cluster and the NoC with low latency. The main focus is the comparison of different memory architectures and their connection to the NoC. We analyze memory architectures with local data memory only, shared data memory only, and a hybrid architecture integrating both. Implementation results are presented for a 28 nm FD-SOI standard cell technology. A CPU cluster with shared memory shows similar area requirements compared to the local memory architecture. We use post place and route simulations for precise analysis of energy consumption on both cluster and NoC level using the different memory architectures. An architecture with shared data memory shows best performance results in combination with a high resource efficiency. On average, the use of shared memory shows a 17.2 percent higher throughput for a benchmark suite of 10 applications compared to the use of local memory only.

Brain-Computer Interfaces (BCIs) based on Steady-State Visually Evoked Potentials (SSVEPs) can be used as hand-free control device. To utilize this control method in a real life scenario, we created a system in which a smart home is controlled by BCI. Six devices in the smart home environment could be controlled with the BCI system: The entrance door, the wardrobe, the kitchens’ worktop and drawers, the light system of all the rooms and a guide light. In the presented paper, the visual stimuli for the BCI were placed at multiple screens in the smart home (placed at different locations such as the kitchen and the living room). The processing was done on one computer, located in the living room. The placement of the visual stimuli corresponded to the actuators that were controlled, e.g. the kitchen drawers were linked to the stimuli displayed in the kitchen. An online experiment was conducted where participants went through a scenario consisting of thirteen SSVEP-BCI selections in total. Eight healthy participants took part in the experiments. For BCI signal acquisition, a mobile EEG amplifier was used. Participants walked freely around the rooms during the experiment. An average accuracy of 81 % was achieved, which suggests that the SSVEP-system is suitable to control the external devices in the smart home, and that the system can be expanded to involve more actuators.

In recent years, subthreshold operation has become a research focus for digital systems with limited energy budget (e.g. mobile, battery-powered devices, radio frequency identification (RFID), wireless sensor networks, or biomedical applications). Subthreshold operation allows for such low power consumption by reducing the supply voltage of the circuit below the threshold voltage of the transistors. As dynamic power depends quadratically on supply voltage, and static power depends exponentially on supply voltage, considerable power savings are achieved. At the same time propagation delays increase due to reduced transistor currents. Effectively, energy consumption per cycle can typically be reduced by a factor of 10 using subthreshold operation.

In large-scaled Multiprocessor System-on-Chips (MPSoCs) the Globally Asynchronous Locally Synchronous (GALS) design paradigm is widely-used to minimize power consumption. Especially Network-on-Chips (NoCs) utilize several GALS approaches to connect hundreds of CPU cores on a single chip. However, improvements in modern design tools, like the clock concurrent optimization flow (CCOpt-flow), require to rethink the benefit of these GALS-based approach. Therefore, the main focus of this work is the comparison of a synchronous (using CCOpt-flow), a multi-synchronous (mesochronous) and a fully asynchronous NoC design for the usage in hierarchical MPSoCs. In hierarchical MPSoCs multiple CPU cores are tightly coupled to clusters, which in turn are connected via a NoC. As a result, wire length for establishing NoC links between the clusters increases, making a NoC design more challenging. Implementation results for a 28nm FD-SOI standard cell technology have shown that the CCOpt-flow still allows to scale a fully synchronous MPSoCs, with slight drawbacks in maximum clock frequency. Nevertheless, the asynchronous NoC outperforms the other two approaches with respect to performance, power and area requirements. The asynchronous NoC leads to a 3:1% smaller MPSoC design. In addition, the proposed asynchronous NoC router consumes only 53% of the power of a mesochronous router during active communication.

Energy efficient embedded computing enables new application scenarios in mobile devices like software-defined radio and video processing. The hierarchical multiprocessor considered in this work may contain dozens or hundreds of resource efficient VLIW CPUs. Programming this number of CPU cores is a complex task requiring compiler support. The stream programming paradigm provides beneficial properties that help to support automatic partitioning. This work describes a compiler for streaming applications targeting the self-build hierarchical CoreVA-MPSoC multiprocessor platform. The compiler is supported by a programming model that is tailored to fit the streaming programming paradigm. We present a novel simulated-annealing (SA) based partitioning algorithm, called Smart SA. The overall speedup of Smart SA is 12.84 for an MPSoC with 16 CPU cores compared to a single CPU implementation. Comparison with a state of the art partitioning algorithm shows an average performance improvement of 34.07%.