This review paper systematically summarizes the existing literature on utilizing machine learning (ML) techniques for the control and monitoring of electric machine drives. It is anticipated that with the rapid progress in learning algorithms and specialized embedded hardware platforms, machine learning-based data-driven approaches will become standard tools for the automated high-performance control and monitoring of electric drives. Additionally, this paper also provides some outlook toward promoting its widespread application in the industry with a focus on deploying ML algorithms onto embedded system-on-chip (SoC) field-programmable gate array (FPGA) devices.

Today's Field Programmable Gate Arrays (FPGAs) can be reconfigured partially, which makes it possible to share resources between various functional modules (hardware tasks) over time. This concept is well known in the area of conventional operating systems. However, in order to transfer resource sharing concepts to operating systems on FPGAs, several underlying mechanisms have to be developed. One of these mechanisms is to suspend hardware tasks and restart them at another time and/or another area of the FPGA. Addressing this problem, this paper discusses ways to save and restore the state information of a hardware task. Afterwards, an implementation of a state relocation mechanisms is presented that uses the standard configuration port. In contrast to similar approaches, we significantly reduce the amount of readback data by reading only those configuration frames that contain state information. We finally determine the time overhead for task relocation, which is essential for most multitasking concepts, like defragmentation.

An energy-efficient SoC with 32 b subthreshold RISC processor cores, 32 kB conventional cache memory, and 9T ultra-low voltage (ULV) SRAM based on a flexible and extensible architecture was fabricated on a 2.7 mm² test chip in 65 nm low power CMOS. The processor cores are based on a custom standard cell library that was designed using a multiobjective approach to optimize noise margins, switching energy, and propagation delay simultaneously. The cores operate over a supply voltage range from 200 mV (best samples) to 1.2 V with clock frequencies from 10 kHz to 94 MHz at room temperature. The lowest energy consumption per cycle of 9.94 pJ is observed at 325 mV and 133 kHz. A 2 kb ULV SRAM macro achieves minimum energy per operation at averages of 321 mV (0.030 σ/μ), 567 fJ (0.037 σ/μ), and 730 kHz (0.184 σ/μ), for equal number of 32 b read/write operations. The off-chip performance and power management subsystem provides dynamic voltage and frequency scaling (DVFS) combined with an adaptive supply voltage generation for dynamic PVT compensation.

Coherent optical communication systems promise superior performance, but their realization in real time also poses big technical challenges. After an introduction the potential of coherent optical transmission systems is shown as manifested in offline experiments. Then we present key components that are necessary to realize these systems in real time. We review recent achievements in realtime coherent communication and finally present the results of a realtime QPSK transmission system with a 3×3 coupler in the receiver. The achieved BER at a data rate of 1.4 Gbit/s is well below the FEC threshold.

The Two-Way Ranging (TWR) method is commonly used for measuring the distance between two wireless transceiver nodes, especially when clock synchronization between the two nodes is not available. For modeling the time-of-flight (TOF) error between two wireless transceiver nodes in TWR, the existing error model, described in the IEEE 802.15.4-2011 standard, is solely based on clock drift. However, it is inadequate for in-depth comparative analysis between different TWR methods. In this paper, we propose a novel TOF Error Estimation Model (TEEM) for TWR methods. Using the proposed model, we evaluate the comparative analysis between different TWR methods. The analytical results were validated with both numerical simulation and experimental results. Moreover, we demonstrate the pitfalls of the symmetric double-sided TWR (SDS-TWR) method, which is the most highlighted TWR method in the literature because of its highly accurate performance on clock-drift error reduction when reply times are symmetric. We argue that alternative double-sided TWR (AltDS-TWR) outperforms SDS-TWR. The argument was verified with both numerical simulation and experimental evaluation results.