Internet of Things (IoT) is an emerging technology and its applications are flattering amidst many users, as it makes everything easier. As a consequence of its massive growth, security and privacy are becoming crucial issues where the IoT devices are perpetually vulnerable to cyber-attacks. To overcome this issue, intrusion detection and mitigation is accomplished which enhances the security in IoT networks. In this paper, we proposed Blockchain entrenched Bi-level intrusion detection and graph based mitigation framework named as HybridChain-IDS. The proposed work embrace four sequential processes includes time-based authentication, user scheduling and access control, bi-level intrusion detection and attack graph generation. Initially, we perform time-based authentication to authenticate the legitimate users using NIK-512 hashing algorithm, password and registered time are stored in Hybridchain which is an assimilation of blockchain and Trusted Execution Environment (TEE) which enhances data privacy and security. After that, we perform user scheduling using Cheetah Optimization Algorithm (COA) which reduces the complexity and then the access control is provided to authorized users by smart contract by considering their trust and permission level. Then, we accomplish bi-level intrusion detection using ResCapsNet which extracts sufficient features and classified effectively. Finally, risk of the attack is evaluated, and then the attacks graphs are generated by employing Enhanced k-nearest neighbor (KNN) algorithm to identify the attack path. Furthermore, the countermeasures are taken based on the attack risk level and the attack graph is stored in Hybridchain for eventual attack prediction. The implementation of this proposed work is directed by network simulator of NS-3.26 and the performance of the proposed HybridChain-IDS is enumerated based on various performance metrics.

Software-defined networking (SDN) represents a transformative approach to network management, enabling the centralized and programmable control of network infrastructure. This paradigm facilitates enhanced scalability, flexibility, and security in managing complex systems. When integrated with the Internet of Things (IoT), SDN addresses critical challenges such as security and efficient network management, positioning the SDN-IoT paradigm as an emerging and impactful technology in modern networking. The rapid proliferation of IoT applications has led to a significant increase in security threats, posing challenges to the safe operation of IoT systems. Consequently, SDN-IoT-based applications and services have been widely adopted to address these issues and challenges. However, this platform faces critical limitations in ensuring scalability, optimizing energy consumption, and addressing persistent security vulnerabilities. To overcome these issues, we proposed a secure SDN-IoT environment for intrusion detection and prevention using virtual blockchain (V-Block). Initially, IoT users are registered and authenticated to the shadow blockchain nodes using a picture-based authentication mechanism. After that, authenticated user flows validation was provided by considering effective metrics utilizing the Trading-based Evolutionary Game Theory (TEGT) approach. Then, we performed a local risk assessment based on evaluated malicious flows severity and then the attack graph was constructed using an Isomorphism-based Graph Neural Network (IGNN) model. Further, multi-controllers were placed optimally using fox optimization algorithm. The generated global paths were securely stored in the virtual blockchain Finally, the two agents in the multi-controllers were responsible for validating and classifying the incoming suspicious flow packets into normal and malicious packets by considering the operative metrics using the Dueling Deep Q Network (DDQN) algorithm. The presented work was conducted by Network Simulator-3.26 and the different performance matrices were used to itemize the suggested V-Block model based on its malicious traffic, attack detection rate, link failure rate, anomaly detection rate, and scalability.

Software Defined Wireless Sensor Networks (SDWSN) enable flexibility in Wireless Sensor Network (WSN) environments by defining the controllable functions to WSN nodes by the Software Defined Network (SDN) controller. Due to the rapid evolution of SDWSNs, adverse effects also have occurred in terms of interference, energy consumption, and security issues. Several state-of-the-art works lend their utmost best to the SDWSN environment. However, the complete picture (i.e., relatability and security in SDWSN) poses severe challenges. The state-of-the-art issues is addressed in this research by proposing interference-aware Multi-Tier Scheduling for the SDWSN environment (MTS-SDWSN). First, we perform network construction in which the proposed network is constructed in a 2D hexagonal grid structure to resolve the connectivity issue. Upon constructing the network, the SDWSN nodes are clustered and managed to reduce the energy consumption using the Divide Well To Merge Better (DWTMB) algorithm in which the optimal Cluster Leader (CL) is selected based on adequate constraint. The data from the clustered nodes are sent to the Local Base Station (LBS) via CL in which they are scheduled in multi-tier format to diminish the complexity and interference issues. The first tier involved in scheduling among Cluster Members (CMs) and CL using adequate metrics, whereas the successive tiers (i.e., second and third) involved in scheduling among CLs to LBSs and LBSs to Sink Node (SN) are done using the Non-Cooperative Fuzzy Theory (NCFT) method. Last, the scheduled nodes are routed to appropriate destinations using Secure and Optimal Routing Protocol (SORP). The proposed SORP includes the Alibaba and Forty Thieves (AFT) and Multi Criteria Decision Making (MCDM) algorithms for selecting and ranking the optimal routes. Further, the security of the routes is enabled by adopting trust and Moving Target Defense (MTD) mechanisms. The MTD includes route switching among the SDWSN devices and active switch handling using Cycle Generative Adversarial Networks (CGAN) among the switches. The proposed work is implemented using a NS-3.26 simulation tool, and performance of the proposed model and existing works shows that the proposed work outperforms the existing works.

Modern Dynamic Random Access Memory (DRAM) banks are characterized by their ability to work in parallel, enabling concurrent servicing of multiple memory accesses through the interleaved DRAM banks. This attractive feature is supported in modern DRAM systems by employing large-sized pages to exploit the locality that exists in the row-buffers. However, one of the key limiting factors for fully utilizing the Bank-Level Parallelism (BLP) feature is the increased contention among processing cores in multi-core systems. This may result in inefficient utilization of the available localities in row-buffers. This, in turn, leads to a degradation in DRAM performance and significant energy wastage. This is due to the activation of large pages only to access a small amount of data, typically 64 bytes. As a result, the likelihood of encountering critical power and performance timing constraints increases. In this article, we propose a highly parallel DRAM architecture designed to mitigate the adverse effects of increased memory contention in multi-core systems on DRAM performance and energy efficiency. Specifically, the DRAM architecture introduced in this study incorporates cost-effective modifications that reduce resource sharing among DRAM pages within a sub-array. This design enables concurrent access to wordlines of varying sizes belonging to different DRAM pages within the same sub-array of a memory bank. This enhancement in the utilization of the allocated bank’s row-buffer space significantly improves the performance and energy efficiency of DRAM systems by further enhancing intra- and inter-sub-array level parallelism. This also further relaxes critical DRAM timing restrictions and facilitates access to finer DRAM page granularities. Our experimental results for quad-core multi-program workloads showed that the DRAM architecture proposed in this study provides significant improvements in average memory access latency and overall DRAM energy consumption compared to the baseline, outperforming previously proposed mechanisms.

Modern DRAM devices’ performance and energy efficiency are significantly improved when the row-buffer locality is exploited properly. In multi-core architectures, however, the DRAM-based main memory banks used by the processing units, called cores, are shared. Memory interference, also known as memory contention, occurs when many cores contend for simultaneous access to the shared banks. The performance benefits provided by utilizing the available row-buffer locality are diminished by the increased memory contention brought on by the integration of more cores. Large DRAM page sizes are therefore activated in order to access only a tiny amount of data. Poor energy efficiency or wasted opportunity to loosen DRAM power timing restrictions are both downsides to this page over-fetching issue. This study introduces a Fine-Grained Activation (FGA) technique to reduce the number of involved bitlines when accessing DRAM memory. This technique significantly improves the parallelism at the DRAM subarray level to support multiple memory accesses routed to distinct subarrays inside the same memory bank. The FGA technique presented in this research intends to provide large energy savings while simultaneously delivering significant performance gains. Our evaluation findings with 4-core multi-program benchmarks demonstrate that the FGA technique proposed in this paper can significantly improve both DRAM performance and DRAM energy efficiency with a negligible area overhead. In comparison to the baseline, the Half-DRAM page activation mechanism, and the recently suggested FGA mechanism, the proposed technique in this study reduces the average DRAM memory access latency for the evaluated four-core applications by 25.6%, 27.1%, and 14.8%, respectively. Our introduced technique also decreases the DRAM activation power by an average of 47%, 27.1%, and 14.7%, respectively, when compared with the baseline, Half-DRAM technique, and the recently proposed FGA mechanism.

This paper introduces a novel hybrid data steganography method that combines the new techniques of LSB1 and LSB2. The proposed method simplifies data-hiding and extraction operations by utilizing a patch method. A unique Private Key (PK) divides the message into two parts. The first part is processed using the LSB1 method, while the second one is treated with the LSB2 method. The PK information is utilized to create secret keys, namely key1 and key2. The keys are generated by converting two Chaotic Logistic Keys (CLKs) and establishing the sequence of cover Stego bytes for concealing and revealing data. The secret message is protected within a secure key area by utilizing the PK, which improves security by preventing unwanted access. The secret message's effective extraction depends significantly on the PK's content. Any alterations to the key during the extraction step will be deemed unlawful, possibly leading to a compromized secret key. Moreover, the suggested approach is followed and assessed by using different messages. The results are comprehensively studied, ensuring a robust evaluation of the quality, efficiency, and security improvements of the data steganography process. The experimental results confirm the data steganography's quality, efficiency, and security enhancements.