The immense progress in physiological signal acquisition and processing in health monitoring allowed a better understanding of patient disease detection and diagnosis. With the increase in data volume and power consumption, effective data compression, signal acquisition, transmission, and processing techniques are essential, especially in telemonitoring healthcare applications. An emerging research area focuses on integrating Compressed Sensing (CS) with physiological signals to deal with a massive amount of physiological data, transmission bandwidth, and power-saving purposes. A review of compressed sensing for physiological signals is presented in this paper, including electroencephalography (EEG), electrocardiography (EEG), electromyography (EMG), and electrodermal activity (EDA), focusing on the pros and cons of CS in treating such signals and the suitability of CS for hardware implementation. Furthermore, we emphasize performance matrices such as Compression Ratio (CR), Signal to-Noise-Ratio (SNR), Percentage Root-mean-square Difference (PRD), and Processing time to evaluate the performance of CS. We also investigate the current practices, challenges, and opportunities of using CS in healthcare applications.

True random number generators (TRNGs) are fundamentals in many important security applications. Though they exploit randomness sources that are typical of the analog domain, digital-based solutions are strongly required especially when they have to be implemented on Field Programmable Gate Array (FPGA)-based digital systems. This paper describes a novel methodology to easily design a TRNG on FPGA devices. It exploits the runtime capability of the Digital Clock Manager (DCM) hardware primitives to tune the phase shift between two clock signals. The presented auto-tuning strategy automatically sets the phase difference of two clock signals in order to force on one or more flip-flops (FFs) to enter the metastability region, used as a randomness source. Moreover, a novel use of the fast carry-chain hardware primitive is proposed to further increase the randomness of the generated bits. Finally, an effective on-chip post-processing scheme that does not reduce the TRNG throughput is described. The proposed TRNG architecture has been implemented on the Xilinx Zynq XC7Z020 System on Chip (SoC). It passed all the National Institute of Standards and Technology (NIST) SP 800-22 statistical tests with a maximum throughput of 300×106 bit per second. The latter is considerably higher than the throughput of other previously published DCMbased TRNGs.

This paper presents the hardware design of fast and low-cost denoising filters suitable to be exploited in the enabling technologies for Industry 5.0. A novel approximate computing strategy is introduced to reduce the computational complexity of the image denoising operation and to comply with real-time requirements. Firstly, it is demonstrated that the novel approximate approach can be helpfully exploited in the design of reconfigurable denoising filters able to reach image qualities as close as possible to the precise software counterparts. The reconfigurability leads to hardware architectures run-time adaptable to different levels of noise, whereas the adopted approximation strategy limits hardware resources and energy requirements. Quality tests, performed at various image and kernel sizes, and noise standard deviations, demonstrate that the approximate denoising approach presented here reaches PSNR and SSIM comparable with the precise denoise filtering. In comparison with state-of-the-art FPGA-based competitors, the novel filters reduce the resources requirements by up to 70%, achieve frame rates up to 35 times higher, and dissipate more than 45% lower power. When implemented within the XC7Z7020 FPGA device, a 5×5 filter designed as proposed here denoises 512×512 grayscale images using only 1689 LUTs, 2635 Flip-Flops and 32 DSPs. Moreover, it processes up to 926.8 frames per second, consumes just 63mW @ 244MHz and, with a noise standard deviation equal to 10, it achieves an average PSNR of ~ 33dB with an average SSIM of ~ 0.86.

In the last few years, extracting, analyzing and classifying welding defects in radiographic images received a great deal of attention in several industry manufacturing. Nowadays, computer vision affords considerable accuracy in many practical applications, but making automatic processes approachable also in this field is still a challenge. As an example, Convolutional Neural Networks (CNNs) are widely recognized as efficient and accurate classification structures, but, due to the limited availability of specific datasets, training a CNN to classify welding defects is not trivial. This paper presents a new dataset collecting 24,407 radiographic images related to several classes of welding defects: lack of penetration, cracks, porosity and no defect. The proposed dataset of welding defects in radiographic images is released freely to the research community. As an example of application, the dataset has been used to train a customized version of the SqueezeNet CNN obtaining a test accuracy higher than 93%.

Neural Network models most often exploit the SoftMax function in the classification stage for computing probabilities through exponentiation and division operations. To reduce the complexity and the energy consumption of such stage, several hardware-friendly approximation strategies have been disclosed in the recent past. This brief evaluates the effects of an aggressive approximation of the SoftMax layer on both classification accuracy and hardware characteristics. Experimental results demonstrate that the proposed circuit, when implemented in a 28 nm FDSOI technology, saves 65% of silicon area with respect to competitors, dissipating less than 1 pJ. FPGA implementation results confirm a massive energy dissipation reduction with respect to the conventional baseline architecture, without introducing penalties in the Top-1 accuracy.