In this paper, a voltage-scaled SRAM for both error-free and error-tolerant applications is presented that dynamically manages the energy/quality trade-off based on application need. Two variation-resilient techniques, write assist and Error Correcting Code, are selectively applied to bit positions having larger impact on the overall quality, while jointly performing voltage scaling to improve overall energy efficiency. The impact of process variations, voltage and temperature on the energy-quality tradeoff is investigated. A 28 nm CMOS 32 kb SRAM shows 35% energy savings at iso-quality and operates at a supply 220 mV below a baseline voltage-scaled SRAM, at the cost of 1.5% area penalty. The impact of the SRAM quality at the system level is evaluated by adopting a H.264 video decoder as case study.

True random number generators (TRNGs) are fundamentals in many important security applications. Though they exploit randomness sources that are typical of the analog domain, digital-based solutions are strongly required especially when they have to be implemented on Field Programmable Gate Array (FPGA)-based digital systems. This paper describes a novel methodology to easily design a TRNG on FPGA devices. It exploits the runtime capability of the Digital Clock Manager (DCM) hardware primitives to tune the phase shift between two clock signals. The presented auto-tuning strategy automatically sets the phase difference of two clock signals in order to force on one or more flip-flops (FFs) to enter the metastability region, used as a randomness source. Moreover, a novel use of the fast carry-chain hardware primitive is proposed to further increase the randomness of the generated bits. Finally, an effective on-chip post-processing scheme that does not reduce the TRNG throughput is described. The proposed TRNG architecture has been implemented on the Xilinx Zynq XC7Z020 System on Chip (SoC). It passed all the National Institute of Standards and Technology (NIST) SP 800-22 statistical tests with a maximum throughput of 300×106 bit per second. The latter is considerably higher than the throughput of other previously published DCMbased TRNGs.

The demand of ultralow-power circuits has significantly increased in the last few years. Owing to its great potential in energy savings, the use of supply voltage near or below the transistors' threshold voltages has gained particular attention. Designing these kinds of circuits is still a challenge, particularly when latest advanced process technologies are employed. This brief proposes novel analytical delay models for CMOS circuits running in the subthreshold regime. The delay models proposed here take the effects of the process variability and of the transient variation of the transistors' on-current during the switching into account. Owing to this, delays are predicted with accuracy significantly higher than existing accurate delay models. Furthermore, the novel models are also suitable for gates with transistors' stacks.

This paper presents the hardware design of fast and low-cost denoising filters suitable to be exploited in the enabling technologies for Industry 5.0. A novel approximate computing strategy is introduced to reduce the computational complexity of the image denoising operation and to comply with real-time requirements. Firstly, it is demonstrated that the novel approximate approach can be helpfully exploited in the design of reconfigurable denoising filters able to reach image qualities as close as possible to the precise software counterparts. The reconfigurability leads to hardware architectures run-time adaptable to different levels of noise, whereas the adopted approximation strategy limits hardware resources and energy requirements. Quality tests, performed at various image and kernel sizes, and noise standard deviations, demonstrate that the approximate denoising approach presented here reaches PSNR and SSIM comparable with the precise denoise filtering. In comparison with state-of-the-art FPGA-based competitors, the novel filters reduce the resources requirements by up to 70%, achieve frame rates up to 35 times higher, and dissipate more than 45% lower power. When implemented within the XC7Z7020 FPGA device, a 5×5 filter designed as proposed here denoises 512×512 grayscale images using only 1689 LUTs, 2635 Flip-Flops and 32 DSPs. Moreover, it processes up to 926.8 frames per second, consumes just 63mW @ 244MHz and, with a noise standard deviation equal to 10, it achieves an average PSNR of ~ 33dB with an average SSIM of ~ 0.86.

Head mounted displays have made virtual reality accessible to a widespread consumer market, introducing a revolution in many applications. Among the limitations of current head mounted display technology, the need of generating high-resolution images and streaming them at adequate frame rates is one of the most critical. Super-Resolution Convolutional Neural Networks can be exploited to alleviate timing and bandwidth bottlenecks of video streaming by reconstructing high-resolution images locally (i.e. near to the display). However, such techniques involve a significant amount of computations that makes their deployment within area/power constrained wearable devices often unfeasible. This research work originated from the consideration that the human eye can capture details with high acuity only within a certain region, called fovea. Therefore, we designed a custom hardware architecture able to reconstruct high-resolution images by treating foveal and peripheral regions through accurate and inaccurate operations, respectively. Hardware experiments demonstrate the effectiveness of our proposal: a customized Fast Super-Resolution Convolutional Neural Network accelerator realized as described here and implemented on a 28nm process technology is able to process up to 214 Ultra High Definition frames per second, while consuming just 0.51pJ/pixel without compromising the perceptual visual quality, thus achieving a 55% energy reduction and ×14 times higher throughput rate, with respect to state-of-the-art competitors.