The discrete Fourier transform (DFT) is widely employed for multi-beam digital beamforming. The DFT can be efficiently implemented through the use of fast Fourier transform (FFT) algorithms, thus reducing chip area, power consumption, processing time, and consumption of other hardware resources. This paper proposes three new hybrid DFT 1024-point DFT approximations and their respective fast algorithms. These approximate DFT (ADFT) algorithms have significantly reduced circuit complexity and power consumption compared to traditional FFT approaches while trading off a subtle loss in computational precision which is acceptable for digital beamforming applications in RF antenna implementations. ADFT algorithms have not been introduced for beamforming beyond N = 32, but this paper anticipates the need for massively large adaptive arrays for future 5G and 6G systems. Digital CMOS circuit designs for the ADFTs show the resulting improvements in both circuit complexity and power consumption metrics. Simulation results show similar or lower critical path delay with up to 48.5% lower chip area compared to a standard Cooley-Tukey FFT. The time-area and dynamic power metrics are reduced up to 66.0%. The 1024-point ADFT beamformers produce SNR gains between 29.2–30.1 dB, which is a loss of ≤ 0.9 dB SNR gain compared to exact 1024-point DFT beamformers (worst case) realizable at using an FFT.

Emerging millimeter-wave (mmW) wireless systems require beamforming and multiple-input multiple-output (MIMO) approaches in order to mitigate path loss, obstructions, and attenuation of the communication channel. Sharp mmW beams are essential for this purpose and must support baseband bandwidths of at least 1 GHz to facilitate higher system capacity. This paper explores a baseband multi-beamforming method based on the spatial Fourier transform. Approximate computing techniques are used to propose a low-complexity fast algorithm with sparse factorizations that neatly map to integer W/L ratios in CMOS current mirrors. The resulting approximate fast Fourier transform (FFT) can thus be efficiently realized using CMOS analog integrated circuits to generate multiple, parallel mmW beams in both transmit and receive modes. The paper proposes both 8and 16-point approximate-FFT algorithms together with circuit theory and design information for 65-nm CMOS implementations. Post-layout simulations of the 8-point circuit in Cadence Spectre provide well-defined mmW beam shapes, a baseband bandwidth of 2.7 GHz, a power consumption of 70 mW, and a dynamic range >42.2 dB. Preliminary experimental results confirm the basic functionality of the 8-beam circuit. Schematic-level analysis of the 16-beam I/Q version show worst-case and average side lobe levels of -10.2 dB and -12.2 dB at 1 GHz bandwidth, and -9.1 dB and -11.3 dB at 1.5 GHz bandwidth. The proposed multibeam architectures have the potential to reduce circuit area and power requirements while meeting the bandwidth requirements of emerging 5G baseband systems.

A low-complexity approximation for the 16-point DFT and its respective multiplierless fast algorithm is proposed. A receive mode multi-beam phased-array experiment was realized at 2.4 GHz employing a 16-element IQ receiver array that uses the proposed approximate spatial DFT in real-time in order to achieve multi-beam digital beamforming. The 16- beam digital receiver experiment uses a ROACH-2 based Xilinx Virtex-6 FPGA platform for both digital beam computation as well as to perform the multi-receiver analog-to-digital conversion. Receive mode RF beams were measured and compared to the exact DFT (realized with fixed-point multipliers with 8-bit twiddle factors). The measured approximate DFT closely followed the measured beams resulting from the fixed-point conventional DFT implementation. The approximate DFT achieves RF beam performance (mainlobe gain, sidelobes) similar to the DFT at the cost of a small error which would be tolerable for the majority of multi-beam phased-array receivers. The 16-point approximate DFT provides a hardware reduction of ∼70% with respect to FFTs, setting up a low size, weight and power (SWaP) system. The maximum magnitude error of the filter bank response is 0.106 (≍ -20 dB).

The discrete cosine transform (DCT) is a relevant tool in signal processing applications, mainly known for its good decorrelation properties. Current image and video coding standards—such as JPEG and HEVC—adopt the DCT as a fundamental building block for compression. Recent works have introduced low-complexity approximations for the DCT, which become paramount in applications demanding real-time computation and low-power consumption. The design of DCT approximations involves a trade-off between computational complexity and performance. This paper introduces a new multiparametric transform class encompassing the round-off DCT (RDCT) and the modified RDCT (MRDCT), two relevant multiplierless 8-point approximate DCTs. The associated fast algorithm is provided. Four novel orthogonal low-complexity 8-point DCT approximations are obtained by solving a multicriteria optimization problem. The optimal 8-point transforms are scaled to lengths 16 and 32 while keeping the arithmetic complexity low. The proposed methods are assessed by proximity and coding measures with respect to the exact DCT. Image and video coding experiments and hardware realization are performed. The novel transforms perform close to or outperform the current state-of-the-art DCT approximations.

This paper introduced a matrix parametrization method based on the Loeffler discrete cosine transform (DCT) algorithm. As a result, a new class of 8-point DCT approximations was proposed, capable of unifying the mathematical formalism of several 8-point DCT approximations archived in the literature. Pareto-efficient DCT approximations are obtained through multicriteria optimization, where computational complexity, proximity, and coding performance are considered. Efficient approximations and their scaled 16- and 32-point versions are embedded into image and video encoders, including a JPEG-like codec and H.264/AVC and H.265/HEVC standards. Results are compared to the unmodified standard codecs. Efficient approximations are mapped and implemented on a Xilinx VLX240T FPGA and evaluated for area, speed, and power consumption.

This paper proposes a computation method for 2D $8\times 8$ DCT based on algebraic integers. The proposed algorithm is based on the Loeffler 1D DCT algorithm, and is shown to operate with exact computation---i.e., error-free arithmetic---up to the final reconstruction step (FRS). The proposed algebraic integer architecture maintains error-free computations until an entire block of DCT coefficients having size 8x8 is computed, unlike algorithms in the literature which claim to be error-free but in fact introduce arithmetic errors between the column- and row-wise 1D DCT stages in a 2D DCT operation. Fast algorithms are proposed for the final reconstruction step employing two approaches, namely, the expansion factor and dyadic approximation. A digital architecture is also proposed for a particular FRS algorithm, and is implemented on an FPGA platform for on-chip verification. The FPGA implementation operates at 360 MHz, and is capable of a real-time throughput of $3.6\cdot 10^8$ 2D DCTs of size $8\times 8$ every second, with corresponding pixel rate of $2.3 \cdot 10^10$ pixels per second. The digital architecture is synthesized using 180 nm CMOS standard cells and shows a chip area of $7.41 mm^2$. The CMOS design is predicted to operate at 893 MHz clock frequency, at a dynamic power consumption $13.22 \text{mW/MH}z\cdot V_{sup}^2$.