Low power and noise tolerant static random access memory (SRAM) cells are in high demand today. This paper presents a stable differential SRAM cell that consumes low power. The proposed cell has similar structure to conventional 6T SRAM cell with the addition of two buffer transistors, one tail transistor and one complementary word line. Due to stacking effect, the proposed cell achieves lower power dissipation. In this paper, impact of process parameters variations on various design metrics of the proposed cell are presented and compared with conventional differential 6T (D6T), transmission gate-based 8T (TG8T), and single ended 8T (SE8T) SRAM cells. Impact of process variation, like threshold voltage and length, on different design metrics of an SRAM cell like, read static noise margin (RSNM), read access time (T _RA ), and write access time (T _WA ) are also presented. The proposed cell achieves 1.12×/1.43×/5.62× improvement in T _RA compared to TG8T/D6T/SE8T at a penalty of 1.1×/4.88× in T _WA compared to D6T/TG8T and 1.19×/1.18× in read/write power consumption compared to D6T. An improvement of 1.12×/2.15× in RSNM is observed compared to D6T/TG8T. The proposed cell consumes 5.38× less power during hold mode and also shows 2.33x narrower spread in hold power @ V _DD = 0.4 V compared to D6T SRAM cell.

Higher noise tolerance, lower power consumption, and higher reliability are the major design metrics for designing an SRAM cell. It is difficult to achieve an SRAM cell with stable operation at low voltage for low power consumption due to increasing variations in process, voltage, and temperature. It is proved that conventional 6 T fails to maintain its stability in scaled technology, particularly in deep-subthreshold regime. Furthermore, it does not support column bit-interleaving architecture. Therefore, it is very much prone to multibit soft error. In this paper, a double-ended read-decoupled ultralow-power 9-T SRAM cell (LP9T) is proposed, and the proposed cell supports the column bit-interleaving architecture. Because of read-decoupled technique, its noise tolerance is improved. To show the effectiveness of the proposed cell, it is compared with other recently published SRAM cells, namely, fully differential 8 T (FD8T), single-ended read-disturb-free 9 T (SEDF9T), and ultradynamic voltage scalable 10 T (UDVS10T). The proposed cell provides 1.2×/2.3× higher read current IREAD compared with UDVS10T/SEDF9T. Furthermore, LP9T shows 3.8×/11.6× improvement in read delay compared with FD8T/UDVS10T. The proposed cell achieves 3.9× higher noise tolerance capability (i.e., read static noise margin (RSNM)) during read operation compared with FD8T. Moreover, LP9T consumes 2.1×/2.1×/4.9× lower hold power H _Power during hold mode compared with FD8T/UDVS10T/SEDF9T. The proposed cell also exhibits 1.5×/4.3×/1.25× narrower spread (i.e., more reliable) in IREAD/RSNM/H _Power compared with UDVS10T/FD8T/SEDF9T. Furthermore, as the proposed cell supports bit-interleaving architecture, error checking and correction technique can be used to mitigate the issue related to multibit soft error. All these benefits are achieved by the LP9T at a cost of 1.17×/1.17×/1.25× longer write delay compared with FD8T/UDVS10T/SEDF9T.

To achieve improved speed of operation, a higher integration density and lower power dissipation, transistors are being scaled aggressively. This trend has reduced the critical charge of sensitive nodes. As a result, SRAM cells used in the high radiation environment of aerospace have become highly vulnerable to soft errors. In this paper, we propose a soft-error-aware 14T (SEA14T) SRAM cell for aerospace applications. The performance of the proposed cell is assessed by comparing it with other radiation-hardened SRAM cells like QUCCE12T, WE-QUATRO, RHM12T, RHD12T, RSP14T and RHBD14T. The proposed cell can fully recover from a single-event upset, of any strength and polarity, induced at all the sensitive nodes. Simulation results also show that SEA14T can fully recover from a multi-node upset induced at the internal node-pair. The proposed cell exhibits 1.06×/ 1.08×/ 1.36× shorter read delay than QUCCE12T/ WE-QUATRO/ RHBD14T and 1.03×/ 1.09×/ 1.12×/ 1.15×/ 1.17× shorter write delay than RHM12T/ WE-QUATRO/ QUCCE12T/ RSP14T/ RHD12T. It also shows 1.33×/ 1.6×/ 2.4× higher read stability than QUCCE12T/ WE-QUATRO/ RHBD14T and 1.13×/ 1.32×/ 1.37×/ 1.42×/ 1.5× higher write ability than RHM12T/ WE-QUATRO/ QUCCE12T/ RSP14T/ RHD12T. Furthermore, the proposed cell consumes 2.31×/ 2.42×/ 2.55×/ 3.04× lower hold power than RHD12T/ RSP14T/ WE-QUATRO/ QUCCE12T @ V _DD = 1 V. All these improvements are achieved at the cost of a slightly larger area overhead.

Space consists of high-energy particles and high-temperature fluctuations, which causes single event upsets (SEUs). Conventional 6T static random access memory (SRAM) is unable to tolerate this harsh environment in space. Therefore, it is necessary to design an SRAM, which can withstand this harsh environment. In order to mitigate SEUs, a radiation-hardened SRAM cell, named soft-error resilient read decoupled 12T (SRRD12T), is presented in this article. To estimate the relative performance of the proposed cell, it is compared with other contemporary designs, such as RHMN12T, RHMP12T, RHD12T, QUCCE12T, and QUATRO12T, over various important design metrics. SRRD12T can not only recover from SEU induced at any of its sensitive nodes but also from single event multi-node upsets (SEMNUs) induced at its storage node pair. Furthermore, due to the read decoupled design of SRRD12T, it exhibits the highest read stability. In addition to these, SRRD12T shows 1.14×/1.17× shorter write delay than RHD12T/RHMP12T. Moreover, SRRD12T consumes lower hold power and exhibits higher write ability than most of the comparison cells. However, these advantages are obtained by exhibiting a slightly longer read delay.

Modern biomedical applications have created a high demand for low power static random access memory (SRAM). In this article, a reliable low power half-select free-write assist 9T (HFWA9T) cell has been proposed. To analyze the impact of process variations on different design metrics, the proposed cell has been compared with other contemporary designs such as feedback-cutting 7T (7T), fully differential 8T (FD8T), and single-ended disturb free 9T (SEDF9T) cells. The HFWA9T cell exhibits 2.87x /3.37x higher read stability or read static noise margin (RSNM) than that of 7T/FD8T and 1.40x /6.55x higher write ability or write static noise margin (WSNM) than that of FD8T/SEDF9T, 2.90x /2.67x and 1.06x /1.01x /5.05x narrower spread in RSNM and WSNM than that of 7T/FD8T and 7T/FD8T/ SEDF9T cells, respectively. In addition, it shows 1.11x /1.03x narrower spread in read delay (TRA) than that of FD8T/SEDF9T and 1.33x shorter TRA than that of SEDF9T cell. Furthermore, it consumes only 0.67x /0.31x /0.48x of the write power and 0.262x /0.605x /0.90x of the read power, respectively, consumed by 7T/FD8T/SEDF9T, while consuming 0.34x /0.96x of static power consumed by 7T/FD8T cell. For all these improvements, it incurs a penalty of 1.62x /1.78x in write delay (TWA) compared to 7T/SEDF9T and 1.58x /1.58x in TRA compared to 7T/FD8T cell at VDD = 700 mV.

Smaller, lighter, and cost-effective satellite design is a major field of research today. Since such satellites are equipped with limited resources, there is a huge demand for low-power cache memory capable of performing reliably even when subjected to harsh cosmic radiations. To address the same, we have proposed a reliable, power-efficient, half-select-free dynamic loop-cutting write assist 12T (DWA12T) cell. The DWA12T has been compared with other state-of-the-art designs, such as the fully differential 8T (FD8T), single-ended disturb free 9T (SEDF9T), bit-interleaving architecture-implementing 11T (BI11T), differential 12T (D12T), and self-refreshing logic-based 12T (WWL12T) cells to estimate their relative performance in terms of major design metrics under severe process, voltage, and temperature (PVT) variations. The proposed cell exhibits 1.65x/3.03x/1.08x/1.38x shorter write delay (TWA) and 3.81x/1.20x/1.90x/2.13x higher write ability [write margin (WM)] than that of SEDF9T/BI11T/D12T/WWL12T and 1.36x/1.54x/1.22x shorter read delay (TRA) and 6.63x higher read stability [read static noise margin (RSNM)] than that of SEDF9T/BI11T/D12T and FD8T, respectively. Moreover, it consumes 1.05x/1.21x/1.10x/1.81x lower static power (HPWR) than that of FD8T/SEDF9T/D12T/WWL12T while showing 3.44x higher hold stability [hold static noise margin (HSNM)] when compared to BI11T. In addition, the DWA12T cell consumes 1.01x/1.02x/1.04x smaller area than that of BI11T/D12T/WWL12T. Furthermore, DWA12T shows lower susceptibility to soft error when compared to FD8T. These improvements are achieved at the cost of 1.37x/1.13x penalty in TWA/TRA and 6.23x penalty in HPWR when compared to FD8T and BI11T, respectively, at VDD = 0.7 V.