This paper presents a technique for designing a low-power and variability-aware SRAM cell. The cell achieves low power dissipation due to its series-connected tail transistor and read buffers, which offer a stacking effect. This paper studies the impact of process, voltage, and temperature (PVT) variations on most of the design metrics of the SRAM cell and compares the results with standard 6T, 9T, and ST10T (Schmitt trigger based) SRAM cells.

Low power and noise tolerant static random access memory (SRAM) cells are in high demand today. This paper presents a stable differential SRAM cell that consumes low power. The proposed cell has similar structure to conventional 6T SRAM cell with the addition of two buffer transistors, one tail transistor and one complementary word line. Due to stacking effect, the proposed cell achieves lower power dissipation. In this paper, impact of process parameters variations on various design metrics of the proposed cell are presented and compared with conventional differential 6T (D6T), transmission gate-based 8T (TG8T), and single ended 8T (SE8T) SRAM cells. Impact of process variation, like threshold voltage and length, on different design metrics of an SRAM cell like, read static noise margin (RSNM), read access time (T _RA ), and write access time (T _WA ) are also presented. The proposed cell achieves 1.12×/1.43×/5.62× improvement in T _RA compared to TG8T/D6T/SE8T at a penalty of 1.1×/4.88× in T _WA compared to D6T/TG8T and 1.19×/1.18× in read/write power consumption compared to D6T. An improvement of 1.12×/2.15× in RSNM is observed compared to D6T/TG8T. The proposed cell consumes 5.38× less power during hold mode and also shows 2.33x narrower spread in hold power @ V _DD = 0.4 V compared to D6T SRAM cell.

Higher noise tolerance, lower power consumption, and higher reliability are the major design metrics for designing an SRAM cell. It is difficult to achieve an SRAM cell with stable operation at low voltage for low power consumption due to increasing variations in process, voltage, and temperature. It is proved that conventional 6 T fails to maintain its stability in scaled technology, particularly in deep-subthreshold regime. Furthermore, it does not support column bit-interleaving architecture. Therefore, it is very much prone to multibit soft error. In this paper, a double-ended read-decoupled ultralow-power 9-T SRAM cell (LP9T) is proposed, and the proposed cell supports the column bit-interleaving architecture. Because of read-decoupled technique, its noise tolerance is improved. To show the effectiveness of the proposed cell, it is compared with other recently published SRAM cells, namely, fully differential 8 T (FD8T), single-ended read-disturb-free 9 T (SEDF9T), and ultradynamic voltage scalable 10 T (UDVS10T). The proposed cell provides 1.2×/2.3× higher read current IREAD compared with UDVS10T/SEDF9T. Furthermore, LP9T shows 3.8×/11.6× improvement in read delay compared with FD8T/UDVS10T. The proposed cell achieves 3.9× higher noise tolerance capability (i.e., read static noise margin (RSNM)) during read operation compared with FD8T. Moreover, LP9T consumes 2.1×/2.1×/4.9× lower hold power H _Power during hold mode compared with FD8T/UDVS10T/SEDF9T. The proposed cell also exhibits 1.5×/4.3×/1.25× narrower spread (i.e., more reliable) in IREAD/RSNM/H _Power compared with UDVS10T/FD8T/SEDF9T. Furthermore, as the proposed cell supports bit-interleaving architecture, error checking and correction technique can be used to mitigate the issue related to multibit soft error. All these benefits are achieved by the LP9T at a cost of 1.17×/1.17×/1.25× longer write delay compared with FD8T/UDVS10T/SEDF9T.

Modern biomedical applications have created a high demand for low power static random access memory (SRAM). In this article, a reliable low power half-select free-write assist 9T (HFWA9T) cell has been proposed. To analyze the impact of process variations on different design metrics, the proposed cell has been compared with other contemporary designs such as feedback-cutting 7T (7T), fully differential 8T (FD8T), and single-ended disturb free 9T (SEDF9T) cells. The HFWA9T cell exhibits 2.87x /3.37x higher read stability or read static noise margin (RSNM) than that of 7T/FD8T and 1.40x /6.55x higher write ability or write static noise margin (WSNM) than that of FD8T/SEDF9T, 2.90x /2.67x and 1.06x /1.01x /5.05x narrower spread in RSNM and WSNM than that of 7T/FD8T and 7T/FD8T/ SEDF9T cells, respectively. In addition, it shows 1.11x /1.03x narrower spread in read delay (TRA) than that of FD8T/SEDF9T and 1.33x shorter TRA than that of SEDF9T cell. Furthermore, it consumes only 0.67x /0.31x /0.48x of the write power and 0.262x /0.605x /0.90x of the read power, respectively, consumed by 7T/FD8T/SEDF9T, while consuming 0.34x /0.96x of static power consumed by 7T/FD8T cell. For all these improvements, it incurs a penalty of 1.62x /1.78x in write delay (TWA) compared to 7T/SEDF9T and 1.58x /1.58x in TRA compared to 7T/FD8T cell at VDD = 700 mV.