This paper aims to design a high-performance interface readout circuit for MEMS gyroscopes, focusing on the low-noise, fully integrated design of the front-end charge-sensitive amplifier (CSA) within the readout circuit. It first reveals the mechanism by which the voltage-resistance characteristics of the pseudo-resistor used to improve the integration level influence the common-mode voltage, and emphasizes the necessity of stabilizing the input common-mode voltage with the continuous-time CSA in gyroscope systems. Based on this theory, a fully integrated CSA based on input common-mode feedback is proposed. The CSA achieves comprehensive optimization of noise and power consumption by reusing the input common-mode feedback circuit and differential-mode detection circuit. Furthermore, the CSA employs a novel differential pseudo-resistor structure, which reduces the noise, area, and power consumption of this part of the circuit by reusing the pseudo-resistor bias circuits. The paper also presents the specific implementation of the PGA and 4th-order $\Sigma \Delta $ modulator in the readout circuit. The readout circuit is fabricated using a $0.18\mu $ m BCD process and achieves bias instability (BI) and angle random walk (ARW) of 0.11°/h and 0.035°/ $\surd $ Hz, respectively combined with MEMS gyroscope and digital circuits. The CSA achieves a capacitance resolution, power consumption, and area consumption of 7.56zF/ $\surd $ Hz, 1.28mW, and $48720\mu $ m², respectively.

This paper presents a monolithic interface application-specific integrated circuit (ASIC) for a MEMS disk resonator gyroscope (DRG) with low zero-rate output (ZRO) drift and low scale factor (SF) nonlinearity. The ASIC is implemented under a high-precision force-to-balanced (FTR) mode combined with an easily integrable self-excitation drive loop. The ASIC improves the performance in two ways: First, based on an analysis of electrical errors in MEMS DRG performance, a time-domain anti-coupling architecture is proposed to reduce electrical coupling effects on ZRO drift and SF nonlinearity. This architecture also eliminates the need for high-bandwidth signal processing compared to traditional frequency-domain architectures. Second, the first-order linear relationship between ZRO drift and drive amplitude voltage in the FTR mode is analyzed and validated, and a low hardware compensation circuit is designed to correct ZRO drift. The ASIC is fabricated using a $0.35\mu $ m BCD process with a chip area of 4.3 mm $\times 4.2$ mm. Combined with the MEMS structure, it achieves a bias instability (BI), angle random walk (ARW), and SF nonlinearity of 0.018°/h, 0.0055° h, and 108 ppm, respectively.

The widespread adoption of high-precision integrated accelerometers with digital output functionality is evident across both military and civilian applications. This research focuses on the application-specific integrated circuit (ASIC) designed for integrated accelerometers, which employs a switched-capacitor topology. The proposed ASIC exhibits key advantages, including a high signal-to-noise ratio (SNR), broad bandwidth, and exceptional linearity. However, integrated accelerometers face significant information security challenges, particularly in Internet of Things (IoT) applications. To address this issue, this work presents a novel ASIC specifically designed to enhance security by enabling the generation of physically unclonable functions (PUFs) within integrated accelerometers. A unique methodology is introduced to derive PUF responses from digital integrated accelerometers by leveraging their inherent manufacturing variations. These intrinsic process variations provide naturally distinct and highly secure cryptographic keys that are challenging to replicate. The feasibility of this approach is validated through comprehensive simulations and experimental measurements on fabricated chips, demonstrating its effectiveness in secure key generation.

This paper proposes a nonlinear correction method for the magnetic gradient tensor system, aiming to mitigate single sensor errors and misalignment errors within the sensor array during measurement. Initially, the paper establishes a sensor error model based on the mechanism of sensor error generation. Subsequently, the total least squares (TLS) ellipsoid fitting method is employed to solve the sensor error compensation parameters. Following this, the paper introduces the differential evolution (DE) algorithm for the nonlinear correction of misalignment errors within the sensor array. The DE algorithm, when utilized for correcting errors in the magnetic gradient tensor system, demonstrates the ability to adaptively adjust parameters, effectively addressing complex optimization problems to minimize errors. Experimental findings reveal that, even under non-uniform magnetic fields, the sensor outputs exhibit significant improvements in overlap and coaxiality post-correction. Moreover, after undergoing ellipsoid fitting correction, the root mean square error (RMSE) of the total magnetic intensity (TMI) for each magnetic sensor is reduced to below 100 nT. Additionally, the average RMSE of each component within the actual tensor system drops from 6079.15 nT/m to 55.11 nT/m, thereby confirming the effectiveness of the proposed method.

This work presents the design and implementation of a high-precision digital interface ASIC for quartz gyroscopes, featuring structural and circuit optimizations in the drive and detection loops to achieve a low-noise, highly integrated system. The proposed design integrates advanced analog-digital hybrid signal processing techniques, including a low-noise charge-sensitive amplifier (CSA), a fully integrated 90° phase shifter, a data converter, and a digital control and compensation circuit. These innovations effectively mitigate phase noise in the drive loop, electrical noise in the sense loop, and bias instability in the gyroscope system, enabling highly accurate detection of angular rate signals. The ASIC is fabricated using a 0.35 μm CMOS process, in conjunction with a quartz gyroscope structure, achieving an Allan variance bias instability (BI) of 0.344°/hr and an angle random walk (ARW) of 0.022°/√hr. These results highlight the integration, stability, and practicality of the digital ASIC for high-precision quartz gyroscopes, facilitating mass production and scalability for high-precision applications.

To meet the requirements of integrated accelerometers for a high-precision reference voltage under wide supply voltage range, high current drive capability, and low power consumption, this paper presents a bandgap reference operational amplifier (op-amp) circuit implemented in CMOS/BiCMOS technology. The proposed design employs a folded-cascode input stage, a push–pull Class-AB output stage, an adaptive output switching mechanism, and a composite frequency compensation scheme. In addition, overcurrent protection and low-frequency noise suppression techniques are incorporated to balance low static power consumption with high load-driving capability. Simulation results show that, under the typical process corner (TT), with VDD = 3 V and T = 25 °C, the op-amp achieves an output swing of 0.2 V~2.8 V, a low-frequency gain of 102~118 dB, a PSRR of 90 dB at 60 Hz, overcurrent protection of ±25 mA, and a phase margin exceeding 48.8° with a 10 μF capacitive load. Across the entire supply voltage range, the static current remains below 150 μA, while maintaining a line regulation better than 150 μV/V and a load regulation better than 150 μV/mA. These results verify the feasibility of achieving both high drive capability and high stability under stringent power constraints, making the proposed design well-suited as a bandgap reference buffer stage for integrated accelerometers, with strong engineering practicality and potential for broad application.