This paper aims to design a high-performance interface readout circuit for MEMS gyroscopes, focusing on the low-noise, fully integrated design of the front-end charge-sensitive amplifier (CSA) within the readout circuit. It first reveals the mechanism by which the voltage-resistance characteristics of the pseudo-resistor used to improve the integration level influence the common-mode voltage, and emphasizes the necessity of stabilizing the input common-mode voltage with the continuous-time CSA in gyroscope systems. Based on this theory, a fully integrated CSA based on input common-mode feedback is proposed. The CSA achieves comprehensive optimization of noise and power consumption by reusing the input common-mode feedback circuit and differential-mode detection circuit. Furthermore, the CSA employs a novel differential pseudo-resistor structure, which reduces the noise, area, and power consumption of this part of the circuit by reusing the pseudo-resistor bias circuits. The paper also presents the specific implementation of the PGA and 4th-order $\Sigma \Delta $ modulator in the readout circuit. The readout circuit is fabricated using a $0.18\mu $ m BCD process and achieves bias instability (BI) and angle random walk (ARW) of 0.11°/h and 0.035°/ $\surd $ Hz, respectively combined with MEMS gyroscope and digital circuits. The CSA achieves a capacitance resolution, power consumption, and area consumption of 7.56zF/ $\surd $ Hz, 1.28mW, and $48720\mu $ m², respectively.

This paper presents a monolithic interface application-specific integrated circuit (ASIC) for a MEMS disk resonator gyroscope (DRG) with low zero-rate output (ZRO) drift and low scale factor (SF) nonlinearity. The ASIC is implemented under a high-precision force-to-balanced (FTR) mode combined with an easily integrable self-excitation drive loop. The ASIC improves the performance in two ways: First, based on an analysis of electrical errors in MEMS DRG performance, a time-domain anti-coupling architecture is proposed to reduce electrical coupling effects on ZRO drift and SF nonlinearity. This architecture also eliminates the need for high-bandwidth signal processing compared to traditional frequency-domain architectures. Second, the first-order linear relationship between ZRO drift and drive amplitude voltage in the FTR mode is analyzed and validated, and a low hardware compensation circuit is designed to correct ZRO drift. The ASIC is fabricated using a $0.35\mu $ m BCD process with a chip area of 4.3 mm $\times 4.2$ mm. Combined with the MEMS structure, it achieves a bias instability (BI), angle random walk (ARW), and SF nonlinearity of 0.018°/h, 0.0055° h, and 108 ppm, respectively.

High-precision miniaturized micromechanical accelerometers are used extensively in the civilian and military fields. A novel self-test-on-chip method and time-multiplexing feedback method for capacitive accelerometers were proposed in this work. The self-test-on-chip circuit can simulate an acceleration signal to test the harmonic distortion without a high-precision shaker table. Using digital timing control, the time-multiplexing feedback can reduce the coupling between the feedback signal and the detection signal. In addition, a low-noise charge sensing and sigma-delta modulator were designed for a high-precision digital output. The interfaced circuit with fully differential topology was fabricated in a 0.35 $\mu $ m standard complementary metal-oxide semiconductor (CMOS) process. The integrated accelerometers can achieve a power consumption of 7 mW from a 5 V supply at a sampling frequency of 256 kHz, a noise floor of $-$ 140 dBV below 400 Hz. The equivalent input noise voltage density is 250nV/ $\surd $ Hz, corresponding to a reference voltage of 2.5V. It can achieve an equivalent noise acceleration of 0.14 $\mu $ g $\surd $ Hz and a bias instability of 9 $\mu $ g at a bandwidth of 400 Hz, a nonlinearity of 0.13% within $\pm$ 1 g.

The physical unclonable function (PUF) can generate a unique identifier for each chip, ideal for key generation and chip anti-counterfeiting. The reliability of PUF is paramount, and therefore is one of the significant challenges for PUF design. This paper proposes a novel SRAM-and Inverter-based PUF (SI PUF) that can operate as either an SRAM PUF or an inverter PUF, depending on the input configuration signal. A zero-overhead bit configuration strategy (BCS) is proposed to enhance the reliability of PUF. Moreover, the working voltage of the sub-threshold level and the well-designed discharge stage ensure that our SI PUF can operate with low power consumption. The tested results of chips fabricated in 40-nm CMOS show that our SI PUF has only 0.0053% of the worst bit error rate (BER) under working conditions of -50 to 125∘C and 0.75 to 1.5V, with 0.073/0.042 pJ/bit of power consumption. The low BER and energy overhead illustrate that our SI PUF is more suitable for resource-limited devices compared to DAC 2022 and JSSC 2020.

The micro-magnetometers with high-resolution digital output are widely used in military and civilian fields. We proposed a novel high-precision interface circuit with optimized chopper technique and switched-capacitor modulator for tunneling magnetoresistance (TMR) sensors. This work also proposes a novel method to create lightweight physically unclonable function (PUF) by using existing TMR devices. The sigma-delta modulator converts the sensor signal into a robust digital output and maintain the signal-to-noise ratio (SNR) of the front-end circuit. We also take advantage of inherent variations of TMR sensors to generate PUF responses that are similarly unique and unclonable. The interface circuit is fabricated by 0.35μm CMOS process from Shanghai Huahong foundry. The active area of ASIC is only about 3 mm×2.7 mm. The interface circuit can achieve a SFDR of 120dB and a SNR of 98 dB at a sampling frequency of 200kHz. The TMR magnetometers were tested in an environment of three-layer magnetic shielding. Our proposed PUF is also tested in terms of uniqueness and reliability.

In order to solve the problems of gas sensor network vulnerability and insufficient reliability of sensor PUF in the Internet of Things (IoT), this paper proposes a highly reliable Reconfiguration Sensor Physical Unclonable Function (RS-PUF) design scheme based on reconfigurable gas sensor arrays through the study of process deviation and physical unclonable function of gas sensor preparation. In this paper, we first prepare a gas sensor using ZnO-SnO ₂ nanomaterials with composite morphology of nanoparticles and nanofibers; then we use the gas sensor to build a reconfigurable gas sensor array and propose a reconfigurable strategy to generate the PUF response; finally, we evaluate the designed PUF for safety and reliability. The experimental results show that the gas sensor has a PUF uniqueness of 52.4%, a randomness of 99.1% and a reliability of 98.17%.