Luis Elias Salgado Solano

Ms. Luis Elias Salgado Solano


Research Focus & Metrics

Academic Career Length

2Years (2025-Present)

(Calculated once Scilit publication data is synced: current year − year of first publication + 1)

Representative Publications

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12 October 2026 in Electronics
Verified
Journal Article
Open access
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LSLuis Elias Salgado Solano
Luis Elias Salgado Solano
FCFelipe Gómez Castañeda
Felipe Gómez Castañeda
LFLuis Martin Flores-Nava
Luis Martin Flores-Nava
Carlos A. Hernández-GutiérrezCarlos A. Hernández-Gutiérrez
Carlos A. Hernández-Gutiérrez
Spiking neural networks (SNNs) are numerical models whose computational properties come from interconnected biological neurons and synapses, leading to the development of neuromorphic systems in either software or hardware. These models in digital hardware operate in the discrete time domain, computing mainly the membrane potential of a neuron, where the arithmetic processes can be reduced to additions with minimal loss in accuracy. This advantage comes from approximating the solution of the original differential membrane equation by a recurrent discrete-time algorithm. In this work, we present a discrete-time SNN design using machine learning tools within the PyTorch framework. Its realization with a Field Programmable Gate Array (FPGA) can efficiently classify industrial gases, which are dangerous. It is demonstrated using available datasets created by experimental measurement boards with metal oxide gas sensors that show variability. The SNN model in this work was trained with the Adam optimizer and a weight clipping procedure to enhance convergence, where the classification efficiency was achieved at 95.7%. Then, the synaptic parameters were exported to an optimized FPGA. Three meaningful contributions of this digital neuromorphic system are as follows: (1) the proposed SNN approximates continuous membrane potentials in neurons with simple time series processing modules, (2) the neuron model, which is the Leaky Integrate and Fire (LIF) model with threshold capability, is parallelizable in hardware, and (3) the final SNN hardware prototype demonstrates its performance in terms of energy efficiency in a classification task scheme. Moreover, the final values of the weighting parameters between neurons are well-suited to an analog spiking system, serving as a hardware counterpart to the digital one in this work.

9 October 2025 in Engineering Research Express
Verified
Journal Article
Open access
FCFelipe Gómez Castañeda
Felipe Gómez Castañeda
LSLuis Elias Salgado Solano
Luis Elias Salgado Solano
LFLuis Martin Flores-Nava
Luis Martin Flores-Nava
The ubiquitous classification task is a computing process within current machine learning frameworks, which are based on neural networks. These neural systems are trained using datasets created from technical, scientific or engineering applications, with excellent outcomes. This is because the associated training algorithms are variants of the gradient descending optimization procedure e.g. Adam or Adamax, that cope with local minima; however, they are computationally complex. The Extreme Learning Machine (ELM) neural model relaxes this numerical issue by computing Moore-Penrose matrices as a training method with acceptable performance values. In this context, Field Programmable Gate Array (FPGA) accelerators have been developed for this type of matrices, which include special-purpose cores. Considering the present work, it introduces the standard Widrow-Hoff neural training rule as the key process to compute efficiently Moore-Penrose matrices in classification tasks using the ELM model. Moreover, the use of the vectorial form instead of the matrixial representation for this training rule reduces the hardware resources in the used FPGA, leading to a low-cost system, whose performance in terms of time and accuracy is suitable for moderate matrix sizes in diverse classification problems. To prove this, six datasets from real-world applications were used, i.e. diabetes, cancer, sonar, ionosphere, wine and vehicle, which serve very often as benchmarks in machine learning research. Therefore, the innovation of this work is the use of a neural learning rule for computing Moore-Penrose matrices with a generic FPGA, with three meaningful features as follows. (1) this technique reduces substantially the usage of numerical resources in the FPGA, (2) the used hardware framework is based on standard development prototyping boards, reducing cost and, (3) although the learning algorithm in this FPGA trains in a stochastic manner, the chosen learning rate reduces this effect without affecting convergence velocity.