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Nanmu Hui
Institute of Scientific and Technological Innovation, Shenyang University, Shenyang 110044, China

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Short communication
Published: 13 April 2021 in Energy Reports
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When the renewable energy power is connected to the grid, distortion voltage interference and grid voltage frequency fluctuation will occur, which will cause the inverter output current to be abnormal. So the grid-connected environment of weak grid puts forward higher requirements on the performance of phase-locked loop (PLL). The synchronous reference frame PLL(SRF-PLL) has become a usually adopted method in grid synchronization technique for its simple structure and strong stability. However, the conventional SRF-PLL has insufficient capability to suppress DC offset, which easily causes fundamental frequency and phase oscillations. Therefore, this paper presents a novel generalized integrator(NGI), and according to the presented NGI structure, a modified novel generalized integrator (MNGI) that can eliminate DC offset voltage is proposed. Then a novel PLL based on dual MNGI(DMNGI) is proposed. This method improves the capability of the phase-locked loop to suppress DC offset. At the same time, this paper designs the parameters of the PLL, and the rationality of the novel PLL is tested effectively through the experimental comparison with the other two methods.

ACS Style

Nanmu Hui; Yingying Feng; Xiaowei Han. DC offset elimination method of Phase-locked loop based on novel generalized integrator. Energy Reports 2021, 7, 30 -35.

AMA Style

Nanmu Hui, Yingying Feng, Xiaowei Han. DC offset elimination method of Phase-locked loop based on novel generalized integrator. Energy Reports. 2021; 7 ():30-35.

Chicago/Turabian Style

Nanmu Hui; Yingying Feng; Xiaowei Han. 2021. "DC offset elimination method of Phase-locked loop based on novel generalized integrator." Energy Reports 7, no. : 30-35.

Journal article
Published: 19 March 2020 in IEEE Access
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The phase-locked accuracy of conventional phase-locked method is reduced when the grid voltage contains fundamental frequency negative sequence(FFNS) component, harmonic component, and DC offset component. Aiming at this problem, a novel adaptive notch filter (NANF) is proposed, and a dual NANF (DNANF) structure is designed to eliminate the FFNS component and extract the fundamental frequency positive sequence(FFPS) component based on NANF. Furthermore, dcDNANF with DC offset rejection capability is proposed by adopting DNANF. Then a novel hybrid filter in dq-frame is designed by combining dcDNANF and the cascaded delay signal cancellation operator filter whose delay parameters are 4 and 24 in dq-frame (dqCDSC4,24). Meanwhile, a new SRF-PLL design method is proposed based on the novel hybrid filter. This proposed method employs dqCDSC4,24 to separate the positive and negative sequences of the voltage and eliminate the high frequency harmonics in the grid voltage, and uses dcDNANF to reject the DC offset, so as to achieve the accurate acquisition of the fundamental voltage information under distortion and unbalanced grid. Simulation and experimental results show that compared with the conventional SRF-PLL methods, the proposed method can obtain faster phase tracking speed, better phase-locked effect, fast dynamic response, and better stability.

ACS Style

Nanmu Hui; Zongan Luo; Yingying Feng; Xiaowei Han. A Novel Grid Synchronization Method Based on Hybrid Filter Under Distorted Voltage Conditions. IEEE Access 2020, 8, 65636 -65648.

AMA Style

Nanmu Hui, Zongan Luo, Yingying Feng, Xiaowei Han. A Novel Grid Synchronization Method Based on Hybrid Filter Under Distorted Voltage Conditions. IEEE Access. 2020; 8 (99):65636-65648.

Chicago/Turabian Style

Nanmu Hui; Zongan Luo; Yingying Feng; Xiaowei Han. 2020. "A Novel Grid Synchronization Method Based on Hybrid Filter Under Distorted Voltage Conditions." IEEE Access 8, no. 99: 65636-65648.

Journal article
Published: 06 January 2020 in IEEE Access
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In the new energy grid-connected power generation system, accurately extracting the grid synchronization signals such as the frequency, phase and amplitude of the grid voltage is the basis for effective control. Aiming at the requirements for detecting grid synchronization signals under unbalanced, harmonics and DC offset voltage mixed conditions, a dual second-order complex coefficient filter with DC offset rejection capability (DSOCCFdc) is proposed, combining the approach of moving average filter (MAF), a novel hybrid filter in dq-frame is designed and on the basis of this design a new synchronous reference frame phase locked loop (SRF-PLL) design approach based on the hybrid filter is proposed. The proposed approach employs moving average filter (MAF) to block the high-frequency harmonics in the grid voltage, and uses DSOCCFdc to separate the fundamental frequency positive and negative sequence and reject DC offset. It can accurately extract the synchronization information of the grid fundamental frequency positive sequence. After simulation and experiment verification, it can be confirmed that the proposed PLL can quickly and accurately lock the properties of the grid voltage under adverse grid condition, and also have high detection accuracy and strong robustness to frequency fluctuations.

ACS Style

Nanmu Hui; Yingying Feng; Xiaowei Han. Design of a High Performance Phase-Locked Loop With DC Offset Rejection Capability Under Adverse Grid Condition. IEEE Access 2020, 8, 6827 -6838.

AMA Style

Nanmu Hui, Yingying Feng, Xiaowei Han. Design of a High Performance Phase-Locked Loop With DC Offset Rejection Capability Under Adverse Grid Condition. IEEE Access. 2020; 8 (99):6827-6838.

Chicago/Turabian Style

Nanmu Hui; Yingying Feng; Xiaowei Han. 2020. "Design of a High Performance Phase-Locked Loop With DC Offset Rejection Capability Under Adverse Grid Condition." IEEE Access 8, no. 99: 6827-6838.

Journal article
Published: 02 April 2018 in IEEE Access
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Synchronous reference frame phase locked loop (SRF-PLL) is widely used for grid synchronization and control in grid-connected applications. A major problem with SRF-PLL is how to improve its dynamic performance and filtering capability under complex grid conditions such as unbalance, distortion, and dc offset mixing without affecting its phase tracking performance and stability. In order to achieve this goal, a novel second-order generalized integrator (NSOGI) and a modified NSOGI (MNSOGI) with dc offset rejection capability based on NSOGI are proposed, and then, an effective hybrid filter is designed and incorporated into the inner loop of a SRF-PLL. The proposed hybrid filter is a combination of a dual MNSOGI and a moving average filter (MAF), it can block the fundamental frequency negative sequence component, dc offset component, and the rest of harmonic components in the SRF-PLL input three-phase voltages at the same time with a simple complexity. The proposed PLL in this paper has a faster transient response due to reducing the window length of the MAF. A small-signal model of the proposed PLL is derived. The stability is analyzed, and parameters design guidelines are given. The effectiveness of the proposed PLL is confirmed through simulation experimental results.

ACS Style

Nanmu Hui; Dazhi Wang; Yunlu Li. A Novel Hybrid Filter-Based PLL to Eliminate Effect of Input Harmonics and DC Offset. IEEE Access 2018, 6, 19762 -19773.

AMA Style

Nanmu Hui, Dazhi Wang, Yunlu Li. A Novel Hybrid Filter-Based PLL to Eliminate Effect of Input Harmonics and DC Offset. IEEE Access. 2018; 6 ():19762-19773.

Chicago/Turabian Style

Nanmu Hui; Dazhi Wang; Yunlu Li. 2018. "A Novel Hybrid Filter-Based PLL to Eliminate Effect of Input Harmonics and DC Offset." IEEE Access 6, no. : 19762-19773.

Journal article
Published: 21 March 2018 in Energies
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Synchronous-reference-frame phase-locked loop (SRF-PLL) is widely used in grid synchronization applications. However, under unbalanced, distorted and DC offset mixed grid conditions, its performance tends to worsen. In order to improve the filtering capability of SRF-PLL, a modified three-order generalized integrator (MTOGI) with DC offset rejection capability based on conventional three order generalized integrator (TOGI) and an enhanced delayed signal cancellation (EDSC) are proposed, then dual modified TOGI (DMTOGI) filtering stage is designed and incorporated into the SRF-PLL control loop with EDSC to form a new hybrid filter-based PLL. The proposed PLL can reject the fundamental frequency negative sequence (FFNS) component, DC offset component, and the rest of harmonic components in SRF-PLL input three-phase voltages at the same time with a simple complexity. The proposed PLL in this paper has a faster transient response due to the EDSC reducing the number of DSC operators. A small-signal model of the proposed PLL is derived. The stability is analyzed and parameter design guidelines are given. Experimental results are included to validate the effectiveness and robustness of the proposed PLL.

ACS Style

Nanmu Hui; Dazhi Wang; Yunlu Li. An Efficient Hybrid Filter-Based Phase-Locked Loop under Adverse Grid Conditions. Energies 2018, 11, 703 .

AMA Style

Nanmu Hui, Dazhi Wang, Yunlu Li. An Efficient Hybrid Filter-Based Phase-Locked Loop under Adverse Grid Conditions. Energies. 2018; 11 (4):703.

Chicago/Turabian Style

Nanmu Hui; Dazhi Wang; Yunlu Li. 2018. "An Efficient Hybrid Filter-Based Phase-Locked Loop under Adverse Grid Conditions." Energies 11, no. 4: 703.