Synchronous reference frame phase locked loop (SRF-PLL) is widely used for grid synchronization and control in grid-connected applications. A major problem with SRF-PLL is how to improve its dynamic performance and filtering capability under complex grid conditions such as unbalance, distortion, and dc offset mixing without affecting its phase tracking performance and stability. In order to achieve this goal, a novel second-order generalized integrator (NSOGI) and a modified NSOGI (MNSOGI) with dc offset rejection capability based on NSOGI are proposed, and then, an effective hybrid filter is designed and incorporated into the inner loop of a SRF-PLL. The proposed hybrid filter is a combination of a dual MNSOGI and a moving average filter (MAF), it can block the fundamental frequency negative sequence component, dc offset component, and the rest of harmonic components in the SRF-PLL input three-phase voltages at the same time with a simple complexity. The proposed PLL in this paper has a faster transient response due to reducing the window length of the MAF. A small-signal model of the proposed PLL is derived. The stability is analyzed, and parameters design guidelines are given. The effectiveness of the proposed PLL is confirmed through simulation experimental results.

The synchronous reference frame phase-locked loop (SRF-PLL) is widely used for synchronization applications. However, it suffers from a poor performance under unbalanced and distorted grid conditions. To improve the filtering capability of SRF-PLL, moving average filter (MAF) is incorporated into its control loop at the cost of a slow transient response of PLL in recently published literature. To further improve their dynamic performance without compromising the disturbance rejection capability and stability, a novel PLL based on quasi-type-1 PLL structure is proposed in this paper. A complex notch filter is incorporated into the QT1-PLL to eliminate the fundamental frequency negative sequence voltage component. The window length of MAF in QT1-PLL is reduced. And MAF is responsible for rejecting the rest of harmonics. Parameter design guidelines are suggested to obtain the minimum settling time for both phase jump and frequency jump. The proposed PLL provides a faster transient response with higher stability margins. The effectiveness of the proposed PLL is confirmed through simulation and experimental results and comparison with advanced PLLs.

In order to reduce the pollution caused by coal-fired generating units during the heating season, and promote the wind power accommodation, an electrical and thermal system dispatch model based on combined heat and power (CHP) with thermal energy storage (TES) and demand response (DR) is proposed. In this model, the emission cost of CO₂, SO₂, NO_x, and the operation cost of desulfurization and denitrification units is considered as environmental cost, which will increase the proportion of the fuel cost in an economic dispatch model. Meanwhile, the fuel cost of generating units, the operation cost and investment cost of thermal energy storage and electrical energy storage, the incentive cost of DR, and the cost of wind curtailment are comprehensively considered in this dispatch model. Then, on the promise of satisfying the load demand, taking the minimum total cost as an objective function, the power of each unit is optimized by a genetic algorithm. Compared with the traditional dispatch model, in which the environmental cost is not considered, the numerical results show that the daily average emissions CO₂, SO₂, NO_x, are decreased by 14,354.35 kg, 55.5 kg, and 47.15 kg, respectively, and the wind power accommodation is increased by an average of 6.56% in a week.

For three‐phase power system, the synchronous reference frame (SRF) phase‐locked loop (PLL) is probably the most widely used synchronisation technique under ideal grid condition. However, the presence of dc‐offset causes fundamental frequency oscillations errors in estimated phase. To deal with this problem, delay signal cancellation (DSC) operator is utilised in SRF‐PLL in recent published literature at the cost of slowing down the dynamic behaviour. The aim is to propose a rapid dc‐offset rejection method in three‐phase PLL for grid synchronisation. With the employment of modified DSC operator, the dynamic performance of the conventional DSC‐based PLL is improved. The effectiveness of the proposed method is confirmed through simulation results.