A strategy for the implementation of the output impedance in single‐phase inverters connected in parallel with droop control for uninterruptible power supply applications is proposed in this study. The proposal allows the load current to be distributed in proportion to the power capacity of the inverters connected in parallel, by establishing the magnitude and phase of the output impedance at the fundamental frequency and its harmonics, when the voltage control is performed through odd harmonic repetitive controllers. This is accomplished through the design of an output impedance profile based on the transfer function of a second‐order high‐pass filter and a virtual impedance loop. The proposal achieves a correct operation of the droop control strategy and the proper sharing of the harmonics of the non‐linear load current between the inverters connected in parallel, obtaining reduced values of individual harmonic content and harmonic distortion in the output voltage with reduced processing requirements. The validity of the proposal is verified through a 2 kVA experimental prototype, considering the requirements of the international quality standards IEC62040‐3 and IEC61000‐2‐2, in terms of output voltage regulation, individual harmonic content, and harmonic distortion for inverters operating both in islanded‐mode and in parallel.

En este trabajo se propone una metodología de diseño del sistema de control de un inversor monofásico para aplicaciones en UPS, que permite cumplir con las exigencias de desempeño de las normas internacionales de calidad de energía IEC62040-3 e IEC61000-2-2. El sistema de control consta de un multi-lazo convencional con controladores del tipo Proporcional-Integral-Derivativo y un Controlador Repetitivo en configuración plug-in con multi-rate (MR-OHRC). La propuesta constituye una metodología de diseño del multi-lazo convencional con la que se reduce la impedancia de salida del inversor y complementa el desempeño del MR-OHRC. De este modo se atenúan las variaciones en la tensión de salida como resultado de perturbaciones producidas por cambios súbitos en la corriente de carga y la alimentación de cargas no lineales. Esta estrategia permite además superar las limitaciones de respuesta dinámica y reducir el tiempo de establecimiento del MR-OHRC. La validez de la propuesta se analiza considerando las exigencias de normas internacionales de calidad de energía en relación a la respuesta dinámica, contenido armónico individual y distorsión armónica, en un prototipo experimental de 2kVA.

This paper presents a fault signal reconstruction method for current sensors in an interleaved buck DC–DC converter, utilizing a sliding mode observer (SMO). A filter bank is used to design the observer within an extended-order system, effectively treating sensor faults as actuator faults, which enables precise estimation of the fault signal. Thus, the proposed approach allows for the identification of the faulty sensor and supports the implementation of fault-tolerant strategies. The paper provides an in-depth analysis of current sensor faults, verifies their impact on current balancing control, and demonstrates the challenge of achieving error-free current estimation in one phase using observers. A comprehensive set of simulation results is carried out, validating the method’s effectiveness and showing a strong correlation with theoretical principles.