Substrate integrated coaxial line (SICL) is a kind of planar transmission line, which can guarantee the propagation of transverse electromagnetic mode wave within a wide band. In this paper, a multichannel SICL array with coaxial lines placed in both vertical and horizontal directions is proposed for high-speed parallel data transmission. The adjacent channels of the SICL array share outer conductors for high-density integration. Moreover, the outer conductor is enhanced by metal fence to suppress the crosstalk between adjacent channels of the SICL array. In addition, a quasi-coaxial transition is designed for the proposed SICL array. A systematical design procedure is given to determine the physical dimensions of SICL array with transitions. The SICL array has flat group delay so that data can be transmitted without significant phase distortion. It is suitable for high-density integration and high-speed data transmission due to the low crosstalk and high bandwidth. To verify the advantage of the proposed SICL array, a 15 x 3 channel prototype is designed and fabricated in low temperature co-fired ceramic. The measured S-parameters agree well with the simulated results. The maximum bandwidth of a single channel of the SICL array is up to 56 GHz and the coupling of adjacent channels in the SICL array is less than -30 dB. Data rate of 30 Gb/s is measured for each channel with good eye diagram and low bit error rate, and hence, a total 1.35-Tb/s data rate can be achieved with the proposed 15 x 3 channel SICL array.

Half-mode substrate integrated waveguide (HMSIW) is a high-pass transmission line, which can be easily integrated into planar circuits. Compared with substrate integrated waveguide (SIW), HMSIW features wider relative bandwidth and smaller size. Quadrature phase shift keying (QPSK) scheme can double the signal transmission rate compared with simple mixing scheme. In this work, an HMSIW with 8-24 GHz frequency band is designed and fabricated, and then a high-speed data transmission system using QPSK scheme is implemented based on the HMSIW. Mathematic modeling of the system is provided to analyze time domain response and crosstalk of the system, and then accurate control of the amplitude and the phase is realized by introduction of amplifier and phase shifter. Hence, the amplitude attenuation caused by the loss of the components and phase differences has been compensated, and the crosstalk caused by the phase differences has been eliminated. The above modeling is validated by experimental results. Comparisons are also made between the system with and without the amplifier/phase shifter. It is shown that the system can transmit signal with 15 Gb/s data rate by one physical channel. High data rate and low bit error rate (BER) are obtained in the proposed system.

A high-speed data transmission system using half mode substrate integrated waveguide (HMSIW) is proposed in this paper. The HMSIW transmits the signal by TE_0.5,0 mode so the channel bandwidth is from the cutoff frequency of TE_0.5,0 mode to the cutoff frequency of TE_1.5,0 mode. In contrast, the traditional SIW transmits the signal by TE₁₀ mode and the channel bandwidth is from the cutoff frequency of TE₁₀ mode to the cutoff frequency of TE₂₀ mode. Therefore, the bandwidth of the proposed HMSIW is 2 times larger than that of the traditional SIW with 2 times waveguide width of HMSIW. Comparison between the interconnect systems based on HMSIW and SIW shows that the HMSIW-based interconnect system has a better performance in high-speed data transmission. The data transmission rate of the proposed HMSIW system can reach up to 7.5 Gbps while that of the traditional SIW system is only 5Gbps with the same condition.

This paper introduces a double-layer chiral metamaterial composed of orthogonal S-shaped resonators, designed for multifunctional applications in the terahertz regime. Numerically demonstrated, the metasurface exhibits distinct operational modes. In the transmission mode, it enables broadband dual-channel asymmetric cross-polarization conversion and transmission. Specifically, in forward propagation, Channel 1 (0.49–1.10 THz, 76.7% fractional bandwidth) converts x - to y -polarized waves with an efficiency exceeding 78%, while simultaneously suppressing the reverse conversion. Conversely, Channel 2 (1.44–1.90 THz, 27.5% fractional bandwidth) performs the opposite polarization conversion ( y - to x -polarization) and transmission while suppressing its counterpart. This asymmetric behavior is reversed under backward wave incidence, with a maximum asymmetric transmission coefficient of 0.89. In reflection mode, the structure achieves perfect absorption of CP waves, with absorption ratios as high as 0.995 for RCP and 0.952 for LCP at two distinct frequencies, demonstrating strong chirality. Furthermore, the absorption resonance exhibits a predictable spectral shift in response to variations in the thickness and refractive index of an overlaying analyte film. This sensitivity suggests the platform’s strong potential for high-performance terahertz sensing applications.

The integrated circuit (IC) industry has significantly improved chip performance by continuously reducing the feature sizes, but miniaturization has introduced heat dissipation challenges, especially for the interconnects. By leveraging the similarity between electric and thermal fields, thermal circuits models can be used to estimate the heat transfer of interconnects. Although conventional thermal circuit models of interconnects include vertical heat transfer, they typically neglected horizontal heat transfer. This paper proposes a fast method based on thermal circuits for estimating the transient temperature response of interconnects under electrostatic discharge (ESD) pulses. The proposed model incorporates both left and right heat dissipation paths, providing closer alignment with physical reality. The model employs electrothermal coupling through voltage-controlled current sources, eliminating the need for iterative algorithms. Both constant temperature boundary and convection boundary are included in the model. Finally, the accuracy of the proposed model is validated through LTspice and finite element method. The results demonstrate that the proposed model achieves significant computational time savings while maintaining modelling accuracy. The proposed model achieves a maximum error of 8.5% and minimum error of 1.5%, respectively, while reducing computation time by approximately 98% compared to conventional methods.

Power consumption in interconnects is a critical constraint on performance improvements in integrated circuits. This paper proposes a novel design methodology to minimize loss in interconnects and address this limitation. The approach incorporates air cavities within the substrate to lower the equivalent loss tangent, thereby reducing dielectric losses. Additionally, the inner conductor is engineered with a periodically nonuniform width to maintain stable effective characteristic impedance. To validate the effectiveness of the methodology, it is applied to both a substrate integrated coaxial line (SICL) and a stripline. Simulation results reveal a 9.76% reduction in loss for the SICL and a 19.40% reduction in loss for the stripline, demonstrating significant improvements with wide tolerance. Furthermore, this design methodology can be generalized to other interconnect types, offering the potential for additional power savings.