Power consumption in interconnects is a critical constraint on performance improvements in integrated circuits. This paper proposes a novel design methodology to minimize loss in interconnects and address this limitation. The approach incorporates air cavities within the substrate to lower the equivalent loss tangent, thereby reducing dielectric losses. Additionally, the inner conductor is engineered with a periodically nonuniform width to maintain stable effective characteristic impedance. To validate the effectiveness of the methodology, it is applied to both a substrate integrated coaxial line (SICL) and a stripline. Simulation results reveal a 9.76% reduction in loss for the SICL and a 19.40% reduction in loss for the stripline, demonstrating significant improvements with wide tolerance. Furthermore, this design methodology can be generalized to other interconnect types, offering the potential for additional power savings.