A multi-level 2D Discrete wavelet transform (DWT) architecture for JPEG2000 is proposed, enhancing speed through parallel processing multiple tile blocks. Based on the lifting scheme, folded architecture and unfolded architecture achieving critical path delay with only one multiplier are designed to increase throughput rate. Connecting the folded and unfolded architecture through a pipeline architecture ensures uniform throughput rates across all DWT levels within a singular clock domain. Computational resource consumption is reduced by adjusting the timing to allow one folded architecture to process three tile blocks of three to five levels of DWT, and a transposing module requiring merely six registers is devised to decrease storage resource consumption. The quantization module, crucial for code-word control in JPEG2000, is integrated into the scaling module with minimal additional resource expenditure. Compared to the existing architecture, the analysis demonstrates that the proposed architecture exhibits enhanced hardware efficiency, with a reduction in transistor-delay-product (TDP) of no less than 14.69%. Synthesis results further reveal an area reduction of at least 26.64%, and a decrease in area-delay-product (ADP) by a minimum of 29.89%. Results from FPGA implementation indicate a significant decrease in resource utilization.

In this article, an area-efficient VLSI architecture scheme for high-throughput computation of the 2-D discrete wavelet transform (DWT) is proposed, effectively applied in the context of aircraft cargo hold scenes. The proposed architecture aims to reduce computation and storage resources while maintaining the DWT-IDWT reconstructed image quality for the 9/7 discrete wavelet. The hardware implementation formulae based on the flipping architecture have been modified to reduce RAM storage bit width. By transforming the coefficients of the formula into hardware-friendly values, the required multiplication operations are split into two stages of addition. On this basis, a pipelined architecture is constructed to set the critical path delay (CPD) of the architecture to be close to the delay of a single adder, $T_{a}$ , thereby achieving a high throughput. Compared to existing architectures in the research field, the proposed single-level 2-D DWT architecture achieves resource savings on the field-programmable gate array (FPGA) platform while ensuring good image reconstruction quality. The advantages of the multilevel 2-D DWT are even more pronounced. In the simulation results on the application-specific integrated circuit (ASIC) platform, the proposed architecture reduces computation time by at least 35.54% while achieving a higher level of decomposition, decreases the area-delay product (ADP) by at least 25.41%, and saves a significant amount of energy per image (EPI). Furthermore, the proposed folded architecture achieves close to 100% hardware utilization efficiency (HUE) in multilevel 2-D DWT computations.

In this paper, a simplified efficient 2-D Discrete Wavelet Transform (DWT) architecture based on the lifting scheme is presented. By approximating the multipliers required for the multiplication operations in the Cohen-Daubechies-Feauveau (CDF) 9/7 filter, computational resources are significantly reduced. Additionally, the strip-based scanning method requires minimal storage resources; for single-level 2-D DWT, there is no need for RAM resources that are dependent on image size. This characteristic makes the proposed architecture particularly well-suited for applications in Wireless Visual Sensor Networks (WVSN). The proposed 2-D DWT and IDWT hardware implementation ensure a reconstructed quality exceeding 90.56 dB Peak Signal-to-Noise Ratio (PSNR) for various N×N images with low power consumption.Compared to existing 2-D DWT architectures, our design offers significant advantages, particularly when processing larger block sizes. The area-delay product (ADP) is reduced by at least 10.02%, the energy per image (EPI) decreases by 75.98%, and power consumption is lowered by 53.52%. Furthermore, the circuit performance in the multi-level architecture is outstanding, and the savings in required resources and energy make the proposed architecture highly suitable for applications in Wireless Visual Sensor Networks (WVSN).