Zhuolun Wu

Mr. Zhuolun Wu

orcid

Research Focus & Metrics

Academic Career Length

4Years (2023-Present)

(Calculated once Scilit publication data is synced: current year − year of first publication + 1)

Representative Publications

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17 March 2023 in IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Verified
Journal Article
Closed access
ZWZhuolun Wu
Zhuolun Wu
WZWei Zhang
Wei Zhang
PJPeng Jing
Peng Jing
YLYanyan Liu
Yanyan Liu
Multiple quantization (MQ) encoder is a basic entropy encoder widely used in multimedia encoding systems, especially in JPEG2000 and JBIG2, which play a key role and make outstanding contributions to digital imaging. However, due to its strict serial working characteristics, the MQ encoder has become a key bottleneck restricting the optimization of JPEG2000 encoding performance. Many single ejection encoder architectures use pipeline staging to improve the throughput, but they have all reached their limits. A high-performance MQ encoder based on a novel lookup table is proposed to overcome this bottleneck, which improves the throughput while utilizing reasonable hardware resources and with low-power consumption. Experimental results show that the proposed encoder architecture can encode two symbols per cycle with a throughput of 1204.82 MSymbol/s, and it has a power consumption of only 11.05 mW. Compared with the conventional multi-context coder, the hardware utilization is reduced by 26%, and the hardware utilization efficiency is improved by 16%. Compared with the conventional single-context coder, the throughput is improved by 14.3%, and the power consumption is reduced by 40.1%.

18 October 2024 in IEEE Communications Letters
Verified
Journal Article
Closed access
ZWZhuolun Wu
Zhuolun Wu
WZWei Zhang
Wei Zhang
YWYihan Wang
Yihan Wang
YLYanyan Liu
Yanyan Liu
Reed-Solomon (RS) codes are widely utilized in systems such as digital transmission and storage systems because of their error-correcting capability. Nevertheless, the substantial number of iterative operations inherent to existing RS code recognition algorithms results in a considerable increase in computational complexity. In this letter, a blind recognition algorithm of RS codes based on multiple threshold judgment and the matrix recording is proposed. The multiple threshold judgment method terminates the iterative process when the threshold condition is satisfied, effectively reducing the recognition process’s computational complexity. Meanwhile, the matrix recording method significantly improves the recognition probability. Simulation results show that the false recognition probability of the proposed recognition algorithm is approaching the false recognition bottom bound and achieves a gain of 0.5dB for RS(31,15,8,37) compared to the low-complexity GFFT (LC-GFFT). Under favourable channel conditions, the computational complexity of the proposed recognition algorithm is reduced by 82.74% and 16.79% compared with the existing RS (31,15,8,37) and RS (255,239,8,285) blind recognition algorithms, respectively.

26 November 2024 in Electronics
Verified
Journal Article
Open access
PDF file
QLQitao Li
Qitao Li
WZWei Zhang
Wei Zhang
ZWZhuolun Wu
Zhuolun Wu
YDYuzhou Dai
Yuzhou Dai
YLYanyan Liu
Yanyan Liu
A multi-level 2D Discrete wavelet transform (DWT) architecture for JPEG2000 is proposed, enhancing speed through parallel processing multiple tile blocks. Based on the lifting scheme, folded architecture and unfolded architecture achieving critical path delay with only one multiplier are designed to increase throughput rate. Connecting the folded and unfolded architecture through a pipeline architecture ensures uniform throughput rates across all DWT levels within a singular clock domain. Computational resource consumption is reduced by adjusting the timing to allow one folded architecture to process three tile blocks of three to five levels of DWT, and a transposing module requiring merely six registers is devised to decrease storage resource consumption. The quantization module, crucial for code-word control in JPEG2000, is integrated into the scaling module with minimal additional resource expenditure. Compared to the existing architecture, the analysis demonstrates that the proposed architecture exhibits enhanced hardware efficiency, with a reduction in transistor-delay-product (TDP) of no less than 14.69%. Synthesis results further reveal an area reduction of at least 26.64%, and a decrease in area-delay-product (ADP) by a minimum of 29.89%. Results from FPGA implementation indicate a significant decrease in resource utilization.

20 August 2025 in IEEE Transactions on Communications
Verified
Journal Article
Closed access
ZWZhuolun Wu
Zhuolun Wu
WZWei Zhang
Wei Zhang
YWYihan Wang
Yihan Wang
HWHao Wang
Hao Wang
YLYanyan Liu
Yanyan Liu
This paper proposes a full-blind recognition method that aims to recognize coding parameters from a noisy bitstream of limited BCH and RS codes intercepted in a non-cooperative communication system under harsh channel environments. This paper optimizes the codeword reliability calculation by fully utilizing channel soft information, based on which the single-bit error codewords can be effectively selected from the codeword stream with a high probability. Subsequently, the channel soft information-based single-error correction (CSI-SEC) algorithm is proposed for correcting single-bit error codewords. The blind recognition algorithm, based on the Galois domain Fourier transform (GFFT) with a dual decision-making mechanism, is applied to these corrected codewords and reliable codewords to extract the encoding parameters. Finally, the method’s superiority is demonstrated through comprehensive simulation experiments. Compared to other blind recognition methods based on error correction, the proposed method exhibits enhanced recognition performance, with a cumulative computational complexity of only 39.8% of that of the other methods. Compared to other algorithms for blind recognition of limited intercepted bitstream, the proposed method achieves at least a 3 dB improvement in recognition performance.

27 January 2025 in IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Verified
Journal Article
Closed access
YDYuzhou Dai
Yuzhou Dai
WZWei Zhang
Wei Zhang
LSLin Shi
Lin Shi
QLQitao Li
Qitao Li
ZWZhuolun Wu
Zhuolun Wu
YLYanyan Liu
Yanyan Liu
In this article, an area-efficient VLSI architecture scheme for high-throughput computation of the 2-D discrete wavelet transform (DWT) is proposed, effectively applied in the context of aircraft cargo hold scenes. The proposed architecture aims to reduce computation and storage resources while maintaining the DWT-IDWT reconstructed image quality for the 9/7 discrete wavelet. The hardware implementation formulae based on the flipping architecture have been modified to reduce RAM storage bit width. By transforming the coefficients of the formula into hardware-friendly values, the required multiplication operations are split into two stages of addition. On this basis, a pipelined architecture is constructed to set the critical path delay (CPD) of the architecture to be close to the delay of a single adder, $T_{a}$ , thereby achieving a high throughput. Compared to existing architectures in the research field, the proposed single-level 2-D DWT architecture achieves resource savings on the field-programmable gate array (FPGA) platform while ensuring good image reconstruction quality. The advantages of the multilevel 2-D DWT are even more pronounced. In the simulation results on the application-specific integrated circuit (ASIC) platform, the proposed architecture reduces computation time by at least 35.54% while achieving a higher level of decomposition, decreases the area-delay product (ADP) by at least 25.41%, and saves a significant amount of energy per image (EPI). Furthermore, the proposed folded architecture achieves close to 100% hardware utilization efficiency (HUE) in multilevel 2-D DWT computations.

24 December 2025 in IEEE Communications Letters
Verified
Journal Article
Closed access
HWHao Wang
Hao Wang
ZWZhuolun Wu
Zhuolun Wu
WZWei Zhang
Wei Zhang
YWYihan Wang
Yihan Wang
YLYanyan Liu
Yanyan Liu
This paper proposes a blind recognition method for Reed-Solomon (RS) codes that is both low in complexity and capable of single-error recognition and correction. Existing methods based on the Galois field Fourier transform (GFFT) still rely on error-free polynomials for recognition. The proposed solution to this problem is a blind recognition algorithm with single-error recognition and correction under harsh channel conditions. The approach involves calculating a part of the spectrum, which allows for accurately identifying a received polynomial with a single error and its error position, making it possible due to the property of the finite field of the Galois field, enabling recognition without the need for error-free polynomials. The simulation results demonstrate that the proposed method achieves higher recognition performance with lower computational complexity compared to existing methods.