This brief presents a novel level-shifter circuit for high-frequency high-voltage (HV) gate-drives. The proposed level shifter (LS) is designed based on a capacitive-coupler/current mirror/ latch structure which helps to extend operation voltage of a floating supply into the negative range, achieves sub-ns and constant delay, and consumes very low power from the floating supply. Additionally, common-mode noise cancellers based on a cross-current mirror and transmission gates are also presented to enhance the dV/dt immunity of the LS against slewing of the floating ground. Implemented in 0.18 μm HV BCD-on-SOI (bipolar-CMOS-DMOS on silicon-on-isolator) process, the post-layout simulation of the proposed design shows a delay of 680 ps, 200 V/ns of dV _SSF /dt slew rate immunity, It dissipates no static power and only 8.1 pJ/transition from the floating supply, improving FoM ¹ and FoM ² of the proposed LS by 3 times and 11.7 times compared to respective state-of-the-art works.

Electrothermal actuators are highly advantageous for microelectromechanical systems (MEMS) due to their capability to generate significant force and large displacements. Despite these benefits, their application in reconfigurable conduction line switches is limited, particularly when employing commercial processes. In DC MEMS switches, electrothermal actuators require electrical insulation between the biasing voltage and the transmission line to prevent interference and maintain the integrity of the switch. This work presents a chevron-type electrothermal actuator utilizing a stack of $\mathrm{S}\mathrm{i}{\mathrm{O}}_2/$ Al thin films on a silicon (Si) structural layer beam to create a DC MEMS switch. The design leverages a thin film Al heater to drive the actuator while the $\mathrm{S}\mathrm{i}{\mathrm{O}}_2$ layer provides electrical insulation, suppressing crosstalk with the Si layer. The electrical contact resistance of a Si-to-Si interface was evaluated by applying a controlled current and measuring the resultant voltage. A low contact resistance of 150 Ω was achieved when an initial contact gap of 2.52 μm was closed using an actuator with an actuation voltage of 1.2 V and a current of 205 mA, with a switching speed of less than 5 ms. Factors such as the contact force, the temperature, and the residual device layer etching angle significantly impact the Si-to-Si contact resistance and the switch’s longevity. The switch withstands a breakdown voltage up to 350 V at its terminal contacts. Thus, it will be robust to self-actuation caused by unwanted voltage contributions, making it suitable for high-voltage and harsh environment applications.

This paper proposes and evaluates several OpenCL-based implementations of the Secure Hash Algorithm-3 (SHA-3) co-processor. These implementations are developed based on OpenCL optimization techniques and their impact on throughput and speedup are reported. The experimental results show that the proposed optimization techniques achieve a 310x speedup when compared to an unoptimized baseline implementation. Moreover, the best reported optimized SHA-3 co-processor achieves a 22.36 Gbps throughput, which is 2 times higher than the best previously published SHA-3 implemented using a high-level synthesis tool and even higher than the performance of most previously reported implementations developed using hardware description languages (HDLs). As a result, an efficient OpenCL-based SHA-3 co-processor suitable for FPGA platforms is proposed. To our knowledge, the reported SHA3 co-processor is the first OpenCL implementation targeting an FPGA-based edge computing platform.

The productivity achieved when developing applications on high-performance reconfigurable heterogeneous computing (HPRHC) systems is increased by using the Open Computing Language (OpenCL). However, the hardware produced by OpenCL compilers in field-programmable gate arrays (FPGAs) can result in severe performance bottlenecks that are challenging to solve. The problem is compounded by the fact that the generated netlist details are disorganized, making them mostly unreadable and only partially visible to designers. This paper proposes an in-FPGA instrumentation method and a new framework for extracting the FPGA-cycle-accurate timing performances of OpenCL-based designs. The results clearly show that the chosen execution model for OpenCL-based designs strongly affects the timing performance when it is not properly implemented. Our framework is implemented on an HPRHC platform that contains a CPU and two Arria10 FPGAs, and it is evaluated with a wide variety of benchmarks with different complexities. After testing on the reported benchmarks, the average logic overhead for one inserted instrument is 0.2 % of the total amount of adaptive look-up tables (ALUTs) and 0.1 % of the total registers in an FPGA. This resource utilization is between 1.5 and six times lower than those reported in the best previously published works. The scalability of the framework is also evaluated by inserting up to 50 instruments. The experimental results show that the average logic utilization per instrument is 0.19 % of the ALUTs and 0.17 % of the registers in the FPGA when 50 instruments are inserted.

This article proposes and validates a low complexity multichannel ring-oscillator (RO)-based time-to-digital converter (TDC) architecture for field-programmable gate arrays (FPGAs). Channels of that TDC are mainly composed of look-up Tables (LUTs) configured as embedded memories. The channels share the same ring oscillator. A previously proposed delay tuning method was used to increase the overall accuracy by balancing the TDC channels. Compared to previously reported TDCs, the proposed architecture consumes fewer resources without degrading performances. A nine-channel TDC was implemented in a Zynq-7 Xilinx FPGA. Single-shot precision of 92.7 ps and accuracy of 92.9 ps were achieved, while consuming 1.49% and 1.31% of the available LUTs and FFs of a ZYNQxc7z010-3clg400 Xilinx FPGA, respectively.