We present in this paper a high-precision voltage-controlled oscillators (VCO)-based time-domain (TD) comparator. It involves two identical and linear VCOs to convert the input voltage difference of the comparator into the time/frequency difference. Also, it includes a novel low-power phase frequency detector (PFD) to compare the output frequencies of the VCOs. The proposed PFD technique reduces the problematic effects of missing edges and phase ambiguity in conventional circuits by minimizing dead-zone (DZ)/blind-zone (BZ) and suppressing unwanted output glitches. The TD-comparator prototype is fabricated in a 350 -nm CMOS process having an active area of 0.01 mm2. The comparator consumes 93.65 μ W power from a 3.3 -V supply and provides a conversion rate of 2.7 MHz with 148 $\boldsymbol {\mu }\mathbf {V_{rms}}$ input-referred noise. Measurement results of 5 fabricated chips show an input-referred offset standard deviation of 81.14 ${\mu }\text{V}$ . Stand-alone characteristics measurements of the proposed PFD show a minimized DZ and BZ of less than 12 and 22.7 ps, respectively. With an almost ${\pm 2\pi }$ input phase range, the maximum operating frequency of the PFD is 1.32 GHz.

The growing number of energy-autonomous applications raises the need for reliable DC energy harvesting techniques such as Thermoelectric Generators (TEGs). One key issue, however, is the minimum voltage (40-60 mV) required for start-up in small TEG energy harvesting sources. We review in this paper recent start-up solutions for TEG energy harvesting technologies. Different solutions have been categorized into 5 main approaches: external battery, extra-fabrication-process-based, transformers, multisource energy harvesting, and DC-AC-DC conversion using oscillators. The ”DC-AC-DC conversion ring oscillators” approach is then shown to be the most promising solution in line with DC energy harvesting applications because it offers several advantages over other approaches, such as allowing full integration with good performance, compatibility with regular CMOS technology, and lower cost. Then, its different implementations are discussed and a detailed analysis is provided to identify their respective advantages and limitations.

We present in this paper design considerations and implementation challenges of a proposed versatile SoC/SiP sensor interface intended for industrial applications. The proposed interface involves high-voltage circuits such as class-D power amplifiers, gate drivers, level shifters, and electrical isolators. Also, it includes low-voltage blocks like programmable gain amplifiers and ADCs. In addition, DC-to-DC converters are used to supply the various building blocks of the projected sensor interface. The key challenges for implementing each block are discussed in this paper. Also, the technological aspects to support the proposed SoC/SiP solution are given. Moreover, the different available packaging technologies to implement the intended SiP solution are discussed in addition to the thermal aspects associated with the system packaging.

In this article, the concept of a 22-kW microwave-powered unmanned aerial vehicle is presented. Its system architecture is analyzed and modeled for wirelessly transferring microwave power to the flying UAVs. The microwave system transmitting power at a 35 GHz frequency was found to be suitable for low-cost and compact architectures. The size of the transmitting and receiving systems are optimized to 108 m² and 90 m², respectively. A linearly polarized 4 × 2 rectangular microstrip patch antenna array has been designed and simulated to obtain a high gain, high directivity, and high efficiency in order to satisfy the power transfer requirements. The numerically simulated gain, directivity, and efficiency of the proposed patch antenna array are 13.4 dBi, 14 dBi, and 85%, respectively. Finally, a rectifying system (rectenna) is optimized using the Agilent advanced design system (ADS) software as a microwave power receiving system. The proposed rectenna at the core of the system has an efficiency profile of more than 80% for an RF input power range of 9 to 18 dBm. Moreover, the RF-to-DC conversion efficiency and DC output voltage of the proposed rectenna are 80% and 3.5 V, respectively, for a 10 dBm input power at 35 GHz with a load of 1500 Ω.

We describe in this paper an improved ring voltage-controlled oscillator (VCO) showing a reduced phase noise while allowing an extended frequency tuning range. The phase noise improvement is obtained through the minimized contribution of tuning line noise while maintaining a rail-to-rail swing. The proposed VCO features a linear tuning characteristic yielding a constant gain over a wide range of operating frequencies. An analytical model is extracted resulting in closed-form expressions for the VCO phase noise. Employing the analytical expressions, the contributed noise and phase noise limitations are fully addressed, and all the effective factors are investigated. The VCO prototype was fabricated in a 0.35 $\mu \text{m}$ CMOS process. It consumes 0.903 mW from a 3.3 V supply when running at its maximum oscillation frequency of 9.37 MHz. The measured VCO phase noise is −147.57 dBc/Hz at 1 MHz offset from the 9.37 MHz oscillation frequency, and the circuit occupies a silicon area of 0.005 mm2. A state-variable MATLAB® model of a time-based sensor interface has been developed including the impact of phase noise nonideality. The system-level simulations demonstrate that the PLL-based sensor interface exploiting the proposed VCO characteristics can achieve a 88.43 dB signal-to-noise ratio over a 1-kHz bandwidth.

Digital isolators have been widely used to protect low voltage electronics as well as human safety from high voltage surges. However, conventional isolation links occupy large chip areas. In this article, a novel small-size on- chip digital isolator for medium-bitrate application based on a CMOS integrated Hall-effect sensor is reported. With the proposed approach, the area of the transmitter coil is reduced to lower than 50% of conventional transformers. The architecture reduces the chip area in isolation amplifiers, power control units, DC-DC converters, and clock recovery circuits. It allows the integration of multichannel isolators using two custom integrated circuits with no post-processing. The tested prototype achieves a data transfer rate of 20 Mbps with above 12 kV/ $\mu \text{s}$ of common-mode transient immunity (CMTI). It has 900 V of continuous isolation working voltage, 27 ns propagation delay, and consumes 2.3 mA of static current.