In active-matrix organic light-emitting diode (AMOLED) displays, conventional pixel circuits that compensate for the non-uniformity of the threshold voltage (V_T) of low-temperature polycrystalline silicon thin-film transistors (TFTs) can hardly compensate for variations in other TFT parameters, such as carrier mobility (μ₀), subthreshold swing (SS) and the various effects of parasitic capacitance. In recent high-resolution AMOLED displays, as the current required for OLED pixel driving decreases, the current error rate (CER) caused by the non-uniform TFT parameters increases. In this study, we analyzed the influence of each TFT parameter on the CER using SPICE simulation. Based on our analysis, the origin of the increased CER can be classified into two categories: the charging capability of driving TFT and the capacitive coupling effect of the switching TFT. The SS of the driving TFT and the parasitic capacitance of the switching TFT are major factors that affect the CER in terms of the charging capability and capacitive coupling effect, respectively. Our analysis results can be summarized as follows: The SS value of the driving TFT should be high, and its variation should be small to minimize the CER. The variation in the parasitic capacitance of the switching TFT possibly occurs due to long-term bias conditions, as well as process non-uniformity. Therefore, the stability of TFT should also be confirmed for the prevention of anomalous CER caused by long-term bias stress.

We investigated the effects of O₂ annealing and N₂O plasma surface treatment on polycrystalline silicon (poly-Si) to improve hysteresis of low-temperature polycrystalline silicon (LTPS) thin-film transistors (TFTs). The O₂ annealing surface-treated LTPS TFTs exhibited a reduction in the subthreshold swing (SS). However, hysteresis improvement was not significantly observed compared to the non-treated LTPS TFTs. However, the N₂O plasma surface-treated LTPS TFTs exhibited a greater reduction in SS and hysteresis improvement than the O₂ annealing surface-treated LTPS TFTs. These results originated from the reduction of trap states at the interface between poly-Si and the gate insulator. Compared to O₂ annealing surface treatment, N₂O plasma surface treatment makes the interface more stable because oxygen passivates the trap states and diffuses into poly-Si. However, as radio-frequency (RF) power increased, SS and hysteresis characteristics degraded due to ion bombardment. Consequently, we improved the hysteresis of LTPS TFTs through N₂O plasma surface treatment on poly-Si by optimizing the RF power conditions.

A new pixel circuit based on silicon backplane technologies for organic light-emitting diode (OLED) microdisplays is proposed for a micro-OLED with several thousand pixels per inch (ppi) and several µm pixel pitch. Because the current level of each pixel for the 63rd gray is approximately 1 nA and the minimum voltage unit at mid-gray is approximately 1 mV for high-ppi micro-OLEDs, the pixel circuit must have highly accurate current control ability. The new pixel circuit can precisely control tiny currents by employing a hybrid programming method that combines current and voltage programming. The proposed current programming based on the current mirror can compensate for short-range transistor variations even under small-current conditions, and the capacitive voltage divider can expand the data voltage range N times. A simulation program with integrated circuit emphasis (SPICE) was employed to evaluate circuit operation and performance. The simulation results indicated N times extended input data voltage range and a low current error rate of 5% for an OLED anode variation of 10 mV.

This article presents novel scan driver circuits for active-matrix display panels based on CMOS logic gates and hybrid thin-film transistor (TFT) technology. In the proposed design, the logic and output parts are separated and implemented using distinct methods to address the limitations of amorphous indium gallium zinc oxide (a-IGZO) TFTs and single-channel-type circuits. Two types of scan driver circuits were designed and simulated to meet a refresh rate of 120 Hz and a resolution of $1440\times 2560$ . The fabricated circuits were evaluated by measuring the output voltage waveforms across ten stages under the same simulation conditions, confirming their operational feasibility. The proposed method enhances the flexibility of circuit design for hybrid TFT-based high-resolution display panels.

This study proposes a data voltage compensation scheme that addresses bottom-gate-to-source voltage (V_BGS) differences in double-gate indium-gallium-zinc oxide (IGZO) thin-film transistors (TFTs) used in active-matrix organic light-emitting diode (AMOLED) pixel circuits. The compensation factor is derived from the pixel current equation and applied to the data voltage to correct the source voltage difference between the data writing and emission periods. To validate the approach, double-gate IGZO TFTs and diode-connected 6T1C pixel circuits were fabricated and evaluated under two bottom-gate conditions. The first ties the bottom-gate to the source and therefore can operate in depletion-mode, while the second applies a negative bottom-gate bias and can operate in enhancement-mode. The depletion-mode pixel shows a maximum current error of 35.8% at the 32nd gray level, while the enhancement-mode pixel reduces the maximum error to 9.6%. This value already reflects a maximum anode voltage (V_A) deviation of 0.047 V and the measured β range from − 0.42 to − 0.38, where β denotes the sensitivity of the threshold voltage (V_TH) to V_BGS. Consequently, the proposed scheme suppresses the V_BGS differences and enables accurate current driving across gray levels.

Low-refresh-rate driving is an effective way to reduce the power consumption of active-matrix organic light-emitting diode (AMOLED) displays. However, in conventional low-temperature polycrystalline silicon (LTPS) thin-film transistor (TFT) pixel circuits, leakage current through switching TFTs can disturb the stored gate voltage of the driving TFT during the long emission period. This causes the time-dependent variation in driving current and visible flicker. In this study, a novel pixel circuit for leakage suppression in low-refresh-rate driving is presented. Bias aging was first applied to reduce the leakage current of the LTPS TFT, and a device model was then built from the characteristics measured at 60 °C. Based on this model, the leakage-induced instability of a conventional 7T1C pixel circuit was analyzed. To suppress this effect, a new 8T1C pixel circuit was proposed. The key idea is to reduce the source–drain voltage of the leakage-sensitive switching TFT during the emission period by raising the initial line potential to a level close to the storage node potential. Simulation results show that the proposed circuit greatly reduces the time-dependent variation in both the driving TFT gate voltage and the driving current compared with the conventional 7T1C circuit. Perceptual evaluation based on human visual sensitivity also confirms stable low-refresh-rate operation down to 20 Hz over the practical gray range. These results show that the proposed circuit is an effective solution for moderate low-refresh-rate operation without relying on low-temperature polycrystalline silicon and oxide (LTPO) technology.