To ensure security and stable quality, deeper cybersecurity evaluations are essential for the development of safety features and functionalities in vehicles. Among these, the AEB system is the most relevant. This research presents a comprehensive TARA of the AEB system, emphasizing the identification, validation, and mitigation of major cybersecurity threats and risks. We systematically examine potential attack vectors by utilizing the STRIDE threat model. This approach enables a detailed analysis of each security threat associated with AEB systems, providing insights into how malicious actors could use the attack paths. The assessment aligns with ISO/SAE 21434, which offers a robust framework for risk management in automotive cybersecurity and IT security, ensuring a thorough evaluation of a system’s architecture. By assessing the AEB system’s architecture against these standards, we identify key components and communication pathways that may be particularly prone to cyberattacks. The results of this analysis highlight critical flaws within the AEB framework and propose corrective measures to enhance cybersecurity resilience. This article provides a structured methodology for assessing and mitigating automotive cybersecurity risks in compliance with industry standards, aiming to facilitate the safe implementation of AEB technology and ultimately improve overall vehicle security and safety.

The increasing complexity of digital hardware design poses significant challenges, particularly when using VHDL. Manual VHDL coding is time-consuming, error-prone, and requires highly specialized expertise, making hardware design a demanding and potentially costly process. This work presents a sophisticated Transformer-based large language model that automatically generates VHDL code from highlevel natural-language descriptions, aiming to streamline hardware design, reduce development effort and cost, and make the technology more accessible to users with limited expertise. A curated dataset of VHDL code, extracted from public repositories and enriched with GPT-Neo 1.3B-generated textual descriptions, was used to train the model. The proposed workflow integrates custom tokenization, model training, syntactic and functional validation, and automated evaluation, including pass@k metrics and hardware synthesiz-ability checks. Experimental results demonstrate that the model can generate syntactically correct and functionally valid VHDL code for representative design problems, including register files, RAM modules, 8-bit counters, debouncing circuits, and instruction fetch units.