Satellite and edge computing designers develop algorithms that restrict resource utilization and execution time. Among these design efforts, optimizing Fast Fourier Transform (FFT), key to many tasks, has led mainly to in-place FFT-specific hardware accelerators. Aiming at improving the FFT performance on processors and computing devices with limited resources, the current paper enhances the efficiency of the radix-2 FFT by exploring the benefits of an in-place technique. First, we present the advantages of organizing the single memory bank of processors to store two (2) FFT elements in each memory address and provide parallel load and store of each FFT pair of data. Second, we optimize the floating point (FP) and block floating point (BFP) configurations to improve the FFT Signal-to-Noise (SNR) performance and the resource utilization. The resulting techniques reduce the memory requirements by two and significantly improve the time performance for the overall prevailing BFP representation. The execution of inputs ranging from 1K to 16K FFT points, using 8-bit or 16-bit as FP or BFP numbers, on the space-proven Atmel AVR32 and Vision Processing Unit (VPU) Intel Movidius Myriad 2, the edge device Raspberry Pi Zero 2W and a low-cost accelerator on Xilinx Zynq 7000 Field Programmable Gate Array (FPGA), validates the method’s performance improvement.

The emerging Kolmogorov–Arnold networks (KANs) have set a new standard in machine learning (ML) tasks by prevailing over traditionally deployed multilayer perceptrons (MLPs) thanks to their enhanced interpretability through activation function learning, while they require increased computational complexity and memory footprint. Radial-basis function (RBF)-based KAN models maintain high performance over other variants of KANs with considerable size reduction and consequently more efficient execution. Aiming at effectively supporting the inference of RBF-KANs on Internet-of-Things (IoT) devices, this paper focuses on edge-oriented computing and introduces a soft intellectual property (IP) core, written in hardware description language (HDL), targeting the execution of such networks on all-programmable systems-on-chip (APSoC). The proposed design is fully pipelined and runtime configurable, allowing for real-time inference and latency-sensitive neural network deployment on-the-fly. A testbench reveals up to $43.6\times$ speedup when compared with a commercial edge central processing unit (CPU) and consumes considerably less power. The core’s adaptable design enables efficient allocation of resources and meets diverse throughput demands, making it well-suited for a broad range of IoT applications.